[{"id":3679678,"web_url":"http://patchwork.ozlabs.org/comment/3679678/","msgid":"","list_archive_url":null,"date":"2026-04-21T05:59:32","subject":"Re: [PATCH v3 10/13] hw/riscv/atlantis: Add PCIe controller","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 21/4/26 07:31, Joel Stanley wrote:\n> From: Nicholas Piggin \n> \n> tt-atlantis is likely to use a generic ECAM compatible PCIe memory map,\n> so gpex is not far off the OS programming model\n> \n> Signed-off-by: Nicholas Piggin \n> Signed-off-by: Joel Stanley \n> ---\n> v3: Avoid leaks in the dt string allocation\n> ---\n> include/hw/riscv/tt_atlantis.h | 2 +\n> hw/riscv/tt_atlantis.c | 225 ++++++++++++++++++++++++++++++++-\n> hw/riscv/Kconfig | 2 +\n> 3 files changed, 228 insertions(+), 1 deletion(-)\n\n\n> +static void create_fdt_pcie(void *fdt,\n> + const MemMapEntry *mem_ecam,\n> + const MemMapEntry *mem_pio,\n> + const MemMapEntry *mem_mmio32,\n> + const MemMapEntry *mem_mmio64,\n> + int legacy_irq,\n> + uint32_t aplic_s_phandle,\n> + uint32_t imsic_s_phandle)\n> +{\n> + g_autofree char *name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n> + mem_ecam->base);\n> +\n> + qemu_fdt_setprop_cell(fdt, name, \"#address-cells\", FDT_PCI_ADDR_CELLS);\n> + qemu_fdt_setprop_cell(fdt, name, \"#interrupt-cells\", FDT_PCI_INT_CELLS);\n> + qemu_fdt_setprop_cell(fdt, name, \"#size-cells\", 0x2);\n> + qemu_fdt_setprop_string(fdt, name, \"compatible\", \"pci-host-ecam-generic\");\n> + qemu_fdt_setprop_string(fdt, name, \"device_type\", \"pci\");\n> + qemu_fdt_setprop_cells(fdt, name, \"bus-range\", 0,\n> + mem_ecam->size / PCIE_MMCFG_SIZE_MIN - 1);\n> + qemu_fdt_setprop(fdt, name, \"dma-coherent\", NULL, 0);\n> + qemu_fdt_setprop_cell(fdt, name, \"msi-parent\", imsic_s_phandle);\n> +\n> + qemu_fdt_setprop_sized_cells(fdt, name, \"reg\",\n> + 2, mem_ecam->base,\n> + 2, mem_ecam->size);\n> + if (!(mem_mmio32->base & 0xffffffffUL)) {\n> + /* XXX: this is a silly hack because it would collide with PIO */\n\nCould you explain a bit more?\n\n> + error_report(\"mmio32 base must not be 0 mod 2^32\");\n> + exit(1);\n> + }\n> + uint32_t flags = FDT_PCI_RANGE_MMIO_64BIT | FDT_PCI_RANGE_PREFETCHABLE;\n> + qemu_fdt_setprop_sized_cells(fdt, name, \"ranges\",\n> + 1, FDT_PCI_RANGE_IOPORT,\n> + 2, 0x0,\n> + 2, mem_pio->base,\n> + 2, mem_pio->size,\n> + 1, FDT_PCI_RANGE_MMIO,\n> + 2, (mem_mmio32->base & 0xffffffffUL),\n> + 2, mem_mmio32->base,\n> + 2, mem_mmio32->size,\n> + 1, flags,\n> + 2, mem_mmio64->base,\n> + 2, mem_mmio64->base,\n> + 2, mem_mmio64->size);\n> +\n> + create_pcie_irq_map(fdt, name, legacy_irq, aplic_s_phandle);\n> +}\n\n\n> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\n> index 0601ae1a7494..2ddee591eb90 100644\n> --- a/hw/riscv/Kconfig\n> +++ b/hw/riscv/Kconfig\n> @@ -129,6 +129,8 @@ config TENSTORRENT\n> select DEVICE_TREE\n> select RISCV_NUMA\n> select PVPANIC_MMIO\n> + select PCI\n\nDo not select PCI explicitly, let the bridge (below) do it.\nRationale is this machine does not expose a PCI bus directly,\nthe bridge device does.\n\n> + select PCI_EXPRESS_GENERIC_BRIDGE\n> select SERIAL_MM\n> select RISCV_ACLINT\n> select RISCV_APLIC","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xco9YRDH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::431;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3679758,"web_url":"http://patchwork.ozlabs.org/comment/3679758/","msgid":"","list_archive_url":null,"date":"2026-04-21T09:10:31","subject":"Re: [PATCH v3 10/13] hw/riscv/atlantis: Add PCIe controller","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"content":"On Tue, Apr 21, 2026 at 07:59:32AM +0200, Philippe Mathieu-Daudé wrote:\n> On 21/4/26 07:31, Joel Stanley wrote:\n> > From: Nicholas Piggin \n> > \n> > tt-atlantis is likely to use a generic ECAM compatible PCIe memory map,\n> > so gpex is not far off the OS programming model\n> > \n> > Signed-off-by: Nicholas Piggin \n> > Signed-off-by: Joel Stanley \n> > ---\n> > v3: Avoid leaks in the dt string allocation\n> > ---\n> > include/hw/riscv/tt_atlantis.h | 2 +\n> > hw/riscv/tt_atlantis.c | 225 ++++++++++++++++++++++++++++++++-\n> > hw/riscv/Kconfig | 2 +\n> > 3 files changed, 228 insertions(+), 1 deletion(-)\n> \n> \n> > +static void create_fdt_pcie(void *fdt,\n> > + const MemMapEntry *mem_ecam,\n> > + const MemMapEntry *mem_pio,\n> > + const MemMapEntry *mem_mmio32,\n> > + const MemMapEntry *mem_mmio64,\n> > + int legacy_irq,\n> > + uint32_t aplic_s_phandle,\n> > + uint32_t imsic_s_phandle)\n> > +{\n> > + g_autofree char *name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n> > + mem_ecam->base);\n> > +\n> > + qemu_fdt_setprop_cell(fdt, name, \"#address-cells\", FDT_PCI_ADDR_CELLS);\n> > + qemu_fdt_setprop_cell(fdt, name, \"#interrupt-cells\", FDT_PCI_INT_CELLS);\n> > + qemu_fdt_setprop_cell(fdt, name, \"#size-cells\", 0x2);\n> > + qemu_fdt_setprop_string(fdt, name, \"compatible\", \"pci-host-ecam-generic\");\n> > + qemu_fdt_setprop_string(fdt, name, \"device_type\", \"pci\");\n> > + qemu_fdt_setprop_cells(fdt, name, \"bus-range\", 0,\n> > + mem_ecam->size / PCIE_MMCFG_SIZE_MIN - 1);\n> > + qemu_fdt_setprop(fdt, name, \"dma-coherent\", NULL, 0);\n> > + qemu_fdt_setprop_cell(fdt, name, \"msi-parent\", imsic_s_phandle);\n> > +\n> > + qemu_fdt_setprop_sized_cells(fdt, name, \"reg\",\n> > + 2, mem_ecam->base,\n> > + 2, mem_ecam->size);\n> > + if (!(mem_mmio32->base & 0xffffffffUL)) {\n> > + /* XXX: this is a silly hack because it would collide with PIO */\n> \n> Could you explain a bit more?\n\nAh this is a bit incomplete sorry I didn't catch it earlier. Before the\nmapping was finalised I just added this hacky way to determining PCIe IO\naddress based on the physical address.\n\nThis should just go away and the IO addresses come from a different table.\n\n> \n> > + error_report(\"mmio32 base must not be 0 mod 2^32\");\n> > + exit(1);\n> > + }\n> > + uint32_t flags = FDT_PCI_RANGE_MMIO_64BIT | FDT_PCI_RANGE_PREFETCHABLE;\n> > + qemu_fdt_setprop_sized_cells(fdt, name, \"ranges\",\n> > + 1, FDT_PCI_RANGE_IOPORT,\n> > + 2, 0x0,\n> > + 2, mem_pio->base,\n> > + 2, mem_pio->size,\n> > + 1, FDT_PCI_RANGE_MMIO,\n> > + 2, (mem_mmio32->base & 0xffffffffUL),\n> > + 2, mem_mmio32->base,\n> > + 2, mem_mmio32->size,\n> > + 1, flags,\n> > + 2, mem_mmio64->base,\n> > + 2, mem_mmio64->base,\n> > + 2, mem_mmio64->size);\n> > +\n> > + create_pcie_irq_map(fdt, name, legacy_irq, aplic_s_phandle);\n> > +}\n> \n> \n> > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig\n> > index 0601ae1a7494..2ddee591eb90 100644\n> > --- a/hw/riscv/Kconfig\n> > +++ b/hw/riscv/Kconfig\n> > @@ -129,6 +129,8 @@ config TENSTORRENT\n> > select DEVICE_TREE\n> > select RISCV_NUMA\n> > select PVPANIC_MMIO\n> > + select PCI\n> \n> Do not select PCI explicitly, let the bridge (below) do it.\n> Rationale is this machine does not expose a PCI bus directly,\n> the bridge device does.\n\nGood to know, thank you.\n\nThanks,\nNick","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=UoULwgSi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0GnH17ybz1yGs\n\tfor ; Tue, 21 Apr 2026 19:11:29 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF77y-0002Wr-Cg; Tue, 21 Apr 2026 05:10:42 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wF77w-0002VP-ER\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 05:10:40 -0400","from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from ) id 1wF77u-0001Ey-Oj\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 05:10:40 -0400","by mail-pg1-x52c.google.com with SMTP id\n 41be03b00d2f7-c70f91776fcso1526222a12.0\n for ; Tue, 21 Apr 2026 02:10:38 -0700 (PDT)","from localhost (203-214-45-63.dyn.iinet.net.au. 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charset=iso-8859-1","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"","Received-SPF":"pass client-ip=2607:f8b0:4864:20::52c;\n envelope-from=npiggin@gmail.com; helo=mail-pg1-x52c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3679873,"web_url":"http://patchwork.ozlabs.org/comment/3679873/","msgid":"<20ba60c7-4929-418a-8596-c531243fec99@linaro.org>","list_archive_url":null,"date":"2026-04-21T12:59:43","subject":"Re: [PATCH v3 10/13] hw/riscv/atlantis: Add PCIe controller","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 21/4/26 11:10, Nicholas Piggin wrote:\n> On Tue, Apr 21, 2026 at 07:59:32AM +0200, Philippe Mathieu-Daudé wrote:\n>> On 21/4/26 07:31, Joel Stanley wrote:\n>>> From: Nicholas Piggin \n>>>\n>>> tt-atlantis is likely to use a generic ECAM compatible PCIe memory map,\n>>> so gpex is not far off the OS programming model\n>>>\n>>> Signed-off-by: Nicholas Piggin \n>>> Signed-off-by: Joel Stanley \n>>> ---\n>>> v3: Avoid leaks in the dt string allocation\n>>> ---\n>>> include/hw/riscv/tt_atlantis.h | 2 +\n>>> hw/riscv/tt_atlantis.c | 225 ++++++++++++++++++++++++++++++++-\n>>> hw/riscv/Kconfig | 2 +\n>>> 3 files changed, 228 insertions(+), 1 deletion(-)\n>>\n>>\n>>> +static void create_fdt_pcie(void *fdt,\n>>> + const MemMapEntry *mem_ecam,\n>>> + const MemMapEntry *mem_pio,\n>>> + const MemMapEntry *mem_mmio32,\n>>> + const MemMapEntry *mem_mmio64,\n>>> + int legacy_irq,\n>>> + uint32_t aplic_s_phandle,\n>>> + uint32_t imsic_s_phandle)\n>>> +{\n>>> + g_autofree char *name = g_strdup_printf(\"/soc/pci@%\"HWADDR_PRIX,\n>>> + mem_ecam->base);\n>>> +\n>>> + qemu_fdt_setprop_cell(fdt, name, \"#address-cells\", FDT_PCI_ADDR_CELLS);\n>>> + qemu_fdt_setprop_cell(fdt, name, \"#interrupt-cells\", FDT_PCI_INT_CELLS);\n>>> + qemu_fdt_setprop_cell(fdt, name, \"#size-cells\", 0x2);\n>>> + qemu_fdt_setprop_string(fdt, name, \"compatible\", \"pci-host-ecam-generic\");\n>>> + qemu_fdt_setprop_string(fdt, name, \"device_type\", \"pci\");\n>>> + qemu_fdt_setprop_cells(fdt, name, \"bus-range\", 0,\n>>> + mem_ecam->size / PCIE_MMCFG_SIZE_MIN - 1);\n>>> + qemu_fdt_setprop(fdt, name, \"dma-coherent\", NULL, 0);\n>>> + qemu_fdt_setprop_cell(fdt, name, \"msi-parent\", imsic_s_phandle);\n>>> +\n>>> + qemu_fdt_setprop_sized_cells(fdt, name, \"reg\",\n>>> + 2, mem_ecam->base,\n>>> + 2, mem_ecam->size);\n>>> + if (!(mem_mmio32->base & 0xffffffffUL)) {\n>>> + /* XXX: this is a silly hack because it would collide with PIO */\n>>\n>> Could you explain a bit more?\n> \n> Ah this is a bit incomplete sorry I didn't catch it earlier. Before the\n> mapping was finalised I just added this hacky way to determining PCIe IO\n> address based on the physical address.\n> \n> This should just go away and the IO addresses come from a different table.\n\nAh good, thanks for the explanation.\n\nRegards,\n\nPhil.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=eWLQISza;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0MsF2lyJz1yGt\n\tfor ; Tue, 21 Apr 2026 23:00:17 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFAhl-00061Y-7e; Tue, 21 Apr 2026 08:59:53 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wFAhh-0005zk-BG\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 08:59:49 -0400","from mail-wm1-x333.google.com ([2a00:1450:4864:20::333])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from ) id 1wFAhf-000094-KD\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 08:59:49 -0400","by mail-wm1-x333.google.com with SMTP id\n 5b1f17b1804b1-483487335c2so42909705e9.2\n for ; Tue, 21 Apr 2026 05:59:47 -0700 (PDT)","from [10.193.39.66] (140.170.88.92.rev.sfr.net. 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