[{"id":3680146,"web_url":"http://patchwork.ozlabs.org/comment/3680146/","msgid":"","list_archive_url":null,"date":"2026-04-22T00:04:33","subject":"Re: [PATCH v3 02/13] hw/riscv/boot: Describe discontiguous memory in\n boot_info","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 3:34 PM Joel Stanley wrote:\n>\n> From: Nicholas Piggin \n>\n> Machines that have discontiguous memory may need to adjust where\n> firmware and images are loaded at boot. Provide an interface for\n> machines to describe a discontiguous low/high RAM scheme for this\n> purpose.\n>\n> Signed-off-by: Nicholas Piggin \n> Reviewed-by: Daniel Henrique Barboza \n> Signed-off-by: Joel Stanley \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> include/hw/riscv/boot.h | 7 +++++++\n> hw/riscv/boot.c | 11 +++++++++++\n> 2 files changed, 18 insertions(+)\n>\n> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\n> index f00b3ca12245..115e3222174f 100644\n> --- a/include/hw/riscv/boot.h\n> +++ b/include/hw/riscv/boot.h\n> @@ -28,6 +28,10 @@\n> #define RISCV64_BIOS_BIN \"opensbi-riscv64-generic-fw_dynamic.bin\"\n>\n> typedef struct RISCVBootInfo {\n> + /* First contiguous RAM region. If size is zero then assume entire RAM */\n> + hwaddr ram_low_start;\n> + hwaddr ram_low_size;\n> +\n> ssize_t kernel_size;\n> hwaddr image_low_addr;\n> hwaddr image_high_addr;\n> @@ -43,6 +47,9 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);\n> char *riscv_plic_hart_config_string(int hart_count);\n>\n> void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);\n> +void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n> + RISCVHartArrayState *harts,\n> + hwaddr start, hwaddr size);\n> vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n> hwaddr firmware_end_addr);\n> hwaddr riscv_find_and_load_firmware(MachineState *machine,\n> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\n> index 9086793b7a7b..5c9547429a36 100644\n> --- a/hw/riscv/boot.c\n> +++ b/hw/riscv/boot.c\n> @@ -69,11 +69,22 @@ char *riscv_plic_hart_config_string(int hart_count)\n>\n> void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)\n> {\n> + info->ram_low_start = 0;\n> + info->ram_low_size = 0;\n> info->kernel_size = 0;\n> info->initrd_size = 0;\n> info->is_32bit = riscv_is_32bit(harts);\n> }\n>\n> +void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n> + RISCVHartArrayState *harts,\n> + hwaddr start, hwaddr size)\n> +{\n> + riscv_boot_info_init(info, harts);\n> + info->ram_low_start = start;\n> + info->ram_low_size = size;\n> +}\n> +\n> vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n> hwaddr firmware_end_addr) {\n> if (info->is_32bit) {\n> --\n> 2.47.3\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=W28M92ga;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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