[{"id":3679673,"web_url":"http://patchwork.ozlabs.org/comment/3679673/","msgid":"<9dde1635-ea18-4abd-8ce5-24ac73f21198@linaro.org>","list_archive_url":null,"date":"2026-04-21T05:47:46","subject":"Re: [PATCH v3 03/13] hw/riscv/boot: Account for discontiguous memory\n when loading firmware","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 21/4/26 07:31, Joel Stanley wrote:\n> From: Nicholas Piggin \n> \n> This loads firmware into the first (low) memory range,\n> accounting for machines having discontiguous memory regions.\n> \n> Signed-off-by: Nicholas Piggin \n> Reviewed-by: Daniel Henrique Barboza \n> Signed-off-by: Joel Stanley \n> ---\n> v3: Call riscv_boot_info_init before riscv_find_and_load_firmware in\n> sifive_u\n> ---\n> include/hw/riscv/boot.h | 5 ++++-\n> hw/riscv/boot.c | 18 ++++++++++++------\n> hw/riscv/microchip_pfsoc.c | 6 ++++--\n> hw/riscv/opentitan.c | 6 ++++--\n> hw/riscv/shakti_c.c | 6 +++++-\n> hw/riscv/sifive_u.c | 6 ++++--\n> hw/riscv/spike.c | 6 ++++--\n> hw/riscv/virt.c | 7 ++++---\n> hw/riscv/xiangshan_kmh.c | 6 +++++-\n> 9 files changed, 46 insertions(+), 20 deletions(-)\n> \n> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\n> index 115e3222174f..fb90bf12399e 100644\n> --- a/include/hw/riscv/boot.h\n> +++ b/include/hw/riscv/boot.h\n> @@ -53,13 +53,16 @@ void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n> vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n> hwaddr firmware_end_addr);\n> hwaddr riscv_find_and_load_firmware(MachineState *machine,\n> + RISCVBootInfo *info,\n> const char *default_machine_firmware,\n> hwaddr *firmware_load_addr,\n> symbol_fn_t sym_cb);\n> const char *riscv_default_firmware_name(RISCVHartArrayState *harts);\n> char *riscv_find_firmware(const char *firmware_filename,\n> const char *default_machine_firmware);\n> -hwaddr riscv_load_firmware(const char *firmware_filename,\n> +hwaddr riscv_load_firmware(MachineState *machine,\n> + RISCVBootInfo *info,\n> + const char *firmware_filename,\n> hwaddr *firmware_load_addr,\n> symbol_fn_t sym_cb);\n\nExcept in _init(), this structure should be const, so preferably\n'const RISCVBootInfo *info'. Can be done on a cleanup patch of\ncourse.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=SLCCKum/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0BH83q6nz1yHB\n\tfor ; Tue, 21 Apr 2026 15:48:34 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3xl-0008CG-1d; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::430;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3681234,"web_url":"http://patchwork.ozlabs.org/comment/3681234/","msgid":"","list_archive_url":null,"date":"2026-04-23T01:58:20","subject":"Re: [PATCH v3 03/13] hw/riscv/boot: Account for discontiguous memory\n when loading firmware","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Tue, 21 Apr 2026 at 15:48, Philippe Mathieu-Daudé wrote:\n>\n> On 21/4/26 07:31, Joel Stanley wrote:\n> > From: Nicholas Piggin \n> >\n> > This loads firmware into the first (low) memory range,\n> > accounting for machines having discontiguous memory regions.\n> >\n> > Signed-off-by: Nicholas Piggin \n> > Reviewed-by: Daniel Henrique Barboza \n> > Signed-off-by: Joel Stanley \n> > ---\n> > v3: Call riscv_boot_info_init before riscv_find_and_load_firmware in\n> > sifive_u\n> > ---\n> > include/hw/riscv/boot.h | 5 ++++-\n> > hw/riscv/boot.c | 18 ++++++++++++------\n> > hw/riscv/microchip_pfsoc.c | 6 ++++--\n> > hw/riscv/opentitan.c | 6 ++++--\n> > hw/riscv/shakti_c.c | 6 +++++-\n> > hw/riscv/sifive_u.c | 6 ++++--\n> > hw/riscv/spike.c | 6 ++++--\n> > hw/riscv/virt.c | 7 ++++---\n> > hw/riscv/xiangshan_kmh.c | 6 +++++-\n> > 9 files changed, 46 insertions(+), 20 deletions(-)\n> >\n> > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\n> > index 115e3222174f..fb90bf12399e 100644\n> > --- a/include/hw/riscv/boot.h\n> > +++ b/include/hw/riscv/boot.h\n> > @@ -53,13 +53,16 @@ void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n> > vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n> > hwaddr firmware_end_addr);\n> > hwaddr riscv_find_and_load_firmware(MachineState *machine,\n> > + RISCVBootInfo *info,\n> > const char *default_machine_firmware,\n> > hwaddr *firmware_load_addr,\n> > symbol_fn_t sym_cb);\n> > const char *riscv_default_firmware_name(RISCVHartArrayState *harts);\n> > char *riscv_find_firmware(const char *firmware_filename,\n> > const char *default_machine_firmware);\n> > -hwaddr riscv_load_firmware(const char *firmware_filename,\n> > +hwaddr riscv_load_firmware(MachineState *machine,\n> > + RISCVBootInfo *info,\n> > + const char *firmware_filename,\n> > hwaddr *firmware_load_addr,\n> > symbol_fn_t sym_cb);\n>\n> Except in _init(), this structure should be const, so preferably\n> 'const RISCVBootInfo *info'. Can be done on a cleanup patch of\n> course.\n\nThis was easy enough to fold in.\n\nA future cleanup could make all of the riscv_load_ functions take a const *.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n secure) header.d=jms.id.au header.i=@jms.id.au header.a=rsa-sha256\n header.s=google header.b=ItCyFO5I;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1K5N05Z5z1yDD\n\tfor ; Thu, 23 Apr 2026 11:59:04 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFjKw-0004eG-MD; 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