[{"id":3681230,"web_url":"http://patchwork.ozlabs.org/comment/3681230/","msgid":"<55515ca0-3185-4b5d-9bbb-5da1245b8cc3@linaro.org>","list_archive_url":null,"date":"2026-04-23T01:48:12","subject":"Re: [PATCH v3 05/14] target/arm/mshv: implement -cpu host for MSHV","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/21/26 15:21, Aastha Rawat wrote:\n> This commit enables support for the `-cpu host` option with MSHV\n> accelerator on ARM64. The implementation queries the partition's CPU's\n> ID registers and features via hypervisor interface, allowing to pass all\n> CPU capabilities for the host CPU to the guest.\n> \n> Replace preprocessor config checks with runtime calls to mshv_enabled(),\n> kvm_enabled(), etc. This ensures that the correct accelerator is\n> selected at runtime when both MSHV and KVM are enabled.\n> \n> Signed-off-by: Aastha Rawat \n> ---\n> accel/mshv/mshv-all.c | 3 +-\n> hw/arm/virt.c | 3 +-\n> include/hw/hyperv/hvgdk_mini.h | 17 ++++\n> include/hw/hyperv/hvhdk.h | 10 ++\n> include/system/hw_accel.h | 3 +-\n> target/arm/cpu.c | 6 +-\n> target/arm/cpu64.c | 24 +++--\n> target/arm/mshv/mshv-all.c | 204 +++++++++++++++++++++++++++++++++++++++++\n> target/arm/mshv_arm.h | 18 ++++\n> 9 files changed, 273 insertions(+), 15 deletions(-)\n> \n> diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c\n> index d4cc7f5371..44f35a1463 100644\n> --- a/accel/mshv/mshv-all.c\n> +++ b/accel/mshv/mshv-all.c\n> @@ -400,13 +400,14 @@ static int mshv_init_vcpu(CPUState *cpu)\n> int ret;\n> \n> cpu->accel = g_new0(AccelCPUState, 1);\n> - mshv_arch_init_vcpu(cpu);\n> \n> ret = mshv_create_vcpu(vm_fd, vp_index, &cpu->accel->cpufd);\n> if (ret < 0) {\n> return -1;\n> }\n> \n> + mshv_arch_init_vcpu(cpu);\n> +\n> cpu->accel->dirty = true;\n> \n> return 0;\n> diff --git a/hw/arm/virt.c b/hw/arm/virt.c\n> index 7456614d05..34eb5248a9 100644\n> --- a/hw/arm/virt.c\n> +++ b/hw/arm/virt.c\n> @@ -50,6 +50,7 @@\n> #include \"system/kvm.h\"\n> #include \"system/hvf.h\"\n> #include \"system/whpx.h\"\n> +#include \"system/mshv.h\"\n> #include \"system/qtest.h\"\n> #include \"system/system.h\"\n> #include \"hw/core/loader.h\"\n> @@ -3450,7 +3451,7 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)\n> if (target_aarch64()) {\n> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"cortex-a53\")));\n> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"cortex-a57\")));\n> - if (kvm_enabled() || hvf_enabled()) {\n> + if (kvm_enabled() || hvf_enabled() || mshv_enabled()) {\n> g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME(\"host\")));\n> }\n> }\n> diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\n> index dfe94050f4..d56be0d70f 100644\n> --- a/include/hw/hyperv/hvgdk_mini.h\n> +++ b/include/hw/hyperv/hvgdk_mini.h\n> @@ -48,6 +48,20 @@ typedef enum hv_register_name {\n> HV_ARM64_REGISTER_LR = 0x0002001E,\n> HV_ARM64_REGISTER_PC = 0x00020022,\n> \n> + /* AArch64 System Register Descriptions: ID Registers */\n> + HV_ARM64_REGISTER_ID_MIDR_EL1 = 0x00022000,\n> + HV_ARM64_REGISTER_ID_MPIDR_EL1 = 0x00022005,\n> + HV_ARM64_REGISTER_ID_AA64_PFR0_EL1 = 0x00022020,\n> + HV_ARM64_REGISTER_ID_AA64_PFR1_EL1 = 0x00022021,\n> + HV_ARM64_REGISTER_ID_AA64_ISAR0_EL1 = 0x00022030,\n> + HV_ARM64_REGISTER_ID_AA64_ISAR1_EL1 = 0x00022031,\n> + HV_ARM64_REGISTER_ID_AA64_ISAR2_EL1 = 0x00022032,\n> + HV_ARM64_REGISTER_ID_AA64_MMFR0_EL1 = 0x00022038,\n> + HV_ARM64_REGISTER_ID_AA64_MMFR1_EL1 = 0x00022039,\n> + HV_ARM64_REGISTER_ID_AA64_MMFR2_EL1 = 0x0002203a,\n> + HV_ARM64_REGISTER_ID_AA64_DFR0_EL1 = 0x00022028,\n> + HV_ARM64_REGISTER_ID_AA64_DFR1_EL1 = 0x00022029,\n\nPlease use the actual name of the register and not add the extra _ after AA64.\n\n> -#if defined(CONFIG_KVM)\n> - kvm_arm_set_cpu_features_from_host(cpu);\n> - aarch64_add_sve_properties(obj);\n> -#elif defined(CONFIG_HVF)\n> - hvf_arm_set_cpu_features_from_host(cpu);\n> -#elif defined(CONFIG_WHPX)\n> - whpx_arm_set_cpu_features_from_host(cpu);\n> -#else\n> - g_assert_not_reached();\n> -#endif\n> + if (mshv_enabled()) {\n> + mshv_arm_set_cpu_features_from_host(cpu);\n> + } else if (kvm_enabled()) {\n> + kvm_arm_set_cpu_features_from_host(cpu);\n> + aarch64_add_sve_properties(obj);\n> + } else if (hvf_enabled()) {\n> + hvf_arm_set_cpu_features_from_host(cpu);\n> + } else if (whpx_enabled()) {\n> + whpx_arm_set_cpu_features_from_host(cpu);\n> + } else {\n> + g_assert_not_reached();\n> + }\n\nIf this is because both mshv and kvm can be enabled simultaneously, then this should be a \nseparate patch to transform the ifdef ladder.\n\n> +static void clamp_id_aa64mmfr0_parange_to_ipa_size(int mshv_fd,\n> + ARMISARegisters *isar)\n> +{\n> + uint32_t ipa_size = mshv_arm_get_ipa_bit_size(mshv_fd);\n> + uint64_t id_aa64mmfr0;\n> +\n> + /* Clamp down the PARange to the IPA size the kernel supports. */\n> + uint8_t index = round_down_to_parange_index(ipa_size);\n> + id_aa64mmfr0 = GET_IDREG(isar, ID_AA64MMFR0);\n> + id_aa64mmfr0 = (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index;\n\nid_aa64_mmfr0 = FIELD_DPREG64(id_aa64mmfr0, AA64MMFR0, PARANGE, index);\n\n> + args.in_ptr = (uintptr_t)(in_buffer);\n> + args.out_sz = values_sz;\n> + args.out_ptr = (uintptr_t)(out_buffer);\n\nDrop unnecessary ().\n\n> + args.reps = (uint16_t) n_regs;\n\nUnnecessary cast.\n\n> +static bool mshv_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n> +{\n> + int mshv_fd = mshv_state->fd;\n> + int vm_fd = mshv_state->vm;\n> + int i, ret;\n> + bool success = true;\n> + uint64_t pfr0, pfr1;\n> + gchar *contents = NULL;\n> +\n> + const struct {\n\nstatic\n\n> + hv_register_name name;\n> + int isar_idx;\n> + } regs[] = {\n> + { HV_ARM64_REGISTER_ID_AA64_PFR0_EL1, ID_AA64PFR0_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_PFR1_EL1, ID_AA64PFR1_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_ISAR0_EL1, ID_AA64ISAR0_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_ISAR1_EL1, ID_AA64ISAR1_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_ISAR2_EL1, ID_AA64ISAR2_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_MMFR0_EL1, ID_AA64MMFR0_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_MMFR1_EL1, ID_AA64MMFR1_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_MMFR2_EL1, ID_AA64MMFR2_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_DFR0_EL1, ID_AA64DFR0_EL1_IDX },\n> + { HV_ARM64_REGISTER_ID_AA64_DFR1_EL1, ID_AA64DFR1_EL1_IDX },\n\nPer above, if you use matching names, you can macroize to avoid typos:\n\n#define R(X) { HV_ARM64_REGISTER_##X, X##_IDX }\n\n R(ID_AA64PFR0_EL1),\n R(ID_AA64PFR1_EL1),\n ...\n\n#undef R\n\nAlso, there are a *lot* more id registers.\nAny chance all, or at least more, are defined by MSHV?\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=m5S7HZY3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate 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<20260421-mshv_accel_arm64_supp-v3-5-469f544778ba@linux.microsoft.com>","From":"Richard Henderson ","Content-Language":"en-US","In-Reply-To":"\n <20260421-mshv_accel_arm64_supp-v3-5-469f544778ba@linux.microsoft.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::72c;\n envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n 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