[{"id":3681225,"web_url":"http://patchwork.ozlabs.org/comment/3681225/","msgid":"<66a7a9ef-bdec-44a2-89e3-28cf77d6684b@linaro.org>","list_archive_url":null,"date":"2026-04-23T01:31:15","subject":"Re: [PATCH v3 04/14] target/arm/mshv: implement vcpu state operations\n for ARM64","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/21/26 15:21, Aastha Rawat wrote:\n> Add support for reading and writing ARM64 CPU registers in the MSHV\n> accelerator. This includes functions to set and get registers,\n> initialize and destroy VCPU state, and manage register state\n> synchronization between QEMU and hypervisor.\n> \n> Signed-off-by: Aastha Rawat \n> ---\n> include/hw/hyperv/hvgdk_mini.h | 42 +++++++++++++\n> target/arm/mshv/mshv-all.c | 138 +++++++++++++++++++++++++++++++++++++++++\n> 2 files changed, 180 insertions(+)\n> \n> diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\n> index cb52cc9de2..dfe94050f4 100644\n> --- a/include/hw/hyperv/hvgdk_mini.h\n> +++ b/include/hw/hyperv/hvgdk_mini.h\n> @@ -13,6 +13,46 @@ typedef enum hv_register_name {\n> /* Pending Interruption Register */\n> HV_REGISTER_PENDING_INTERRUPTION = 0x00010002,\n> \n> +#if defined(__aarch64__)\n\nNot ideal, having target/host-specific stuff in a global header.\nThat said, you don't actually need the ifdefs at all.\n\n> + HV_ARM64_REGISTER_XZR = 0x0002FFFE,\n> + HV_ARM64_REGISTER_X0 = 0x00020000,\n> + HV_ARM64_REGISTER_X1 = 0x00020001,\n> + HV_ARM64_REGISTER_X2 = 0x00020002,\n> + HV_ARM64_REGISTER_X3 = 0x00020003,\n> + HV_ARM64_REGISTER_X4 = 0x00020004,\n> + HV_ARM64_REGISTER_X5 = 0x00020005,\n> + HV_ARM64_REGISTER_X6 = 0x00020006,\n> + HV_ARM64_REGISTER_X7 = 0x00020007,\n> + HV_ARM64_REGISTER_X8 = 0x00020008,\n> + HV_ARM64_REGISTER_X9 = 0x00020009,\n> + HV_ARM64_REGISTER_X10 = 0x0002000A,\n> + HV_ARM64_REGISTER_X11 = 0x0002000B,\n> + HV_ARM64_REGISTER_X12 = 0x0002000C,\n> + HV_ARM64_REGISTER_X13 = 0x0002000D,\n> + HV_ARM64_REGISTER_X14 = 0x0002000E,\n> + HV_ARM64_REGISTER_X15 = 0x0002000F,\n> + HV_ARM64_REGISTER_X16 = 0x00020010,\n> + HV_ARM64_REGISTER_X17 = 0x00020011,\n> + HV_ARM64_REGISTER_X18 = 0x00020012,\n> + HV_ARM64_REGISTER_X19 = 0x00020013,\n> + HV_ARM64_REGISTER_X20 = 0x00020014,\n> + HV_ARM64_REGISTER_X21 = 0x00020015,\n> + HV_ARM64_REGISTER_X22 = 0x00020016,\n> + HV_ARM64_REGISTER_X23 = 0x00020017,\n> + HV_ARM64_REGISTER_X24 = 0x00020018,\n> + HV_ARM64_REGISTER_X25 = 0x00020019,\n> + HV_ARM64_REGISTER_X26 = 0x0002001A,\n> + HV_ARM64_REGISTER_X27 = 0x0002001B,\n> + HV_ARM64_REGISTER_X28 = 0x0002001C,\n> + HV_ARM64_REGISTER_FP = 0x0002001D,\n> + HV_ARM64_REGISTER_LR = 0x0002001E,\n> + HV_ARM64_REGISTER_PC = 0x00020022,\n> +\n> + /* AArch64 System Register Descriptions: General system control registers */\n> + HV_ARM64_REGISTER_MIDR_EL1 = 0x00040051,\n> + HV_ARM64_REGISTER_MPIDR_EL1 = 0x00040001,\n> +\n> +#elif defined(__x86_64__)\n\n> +static enum hv_register_name STANDARD_REGISTER_NAMES[32] = {\n\nconst.\n\n> + HV_ARM64_REGISTER_X0,\n> + HV_ARM64_REGISTER_X1,\n> + HV_ARM64_REGISTER_X2,\n> + HV_ARM64_REGISTER_X3,\n> + HV_ARM64_REGISTER_X4,\n> + HV_ARM64_REGISTER_X5,\n> + HV_ARM64_REGISTER_X6,\n> + HV_ARM64_REGISTER_X7,\n> + HV_ARM64_REGISTER_X8,\n> + HV_ARM64_REGISTER_X9,\n> + HV_ARM64_REGISTER_X10,\n> + HV_ARM64_REGISTER_X11,\n> + HV_ARM64_REGISTER_X12,\n> + HV_ARM64_REGISTER_X13,\n> + HV_ARM64_REGISTER_X14,\n> + HV_ARM64_REGISTER_X15,\n> + HV_ARM64_REGISTER_X16,\n> + HV_ARM64_REGISTER_X17,\n> + HV_ARM64_REGISTER_X18,\n> + HV_ARM64_REGISTER_X19,\n> + HV_ARM64_REGISTER_X20,\n> + HV_ARM64_REGISTER_X21,\n> + HV_ARM64_REGISTER_X22,\n> + HV_ARM64_REGISTER_X23,\n> + HV_ARM64_REGISTER_X24,\n> + HV_ARM64_REGISTER_X25,\n> + HV_ARM64_REGISTER_X26,\n> + HV_ARM64_REGISTER_X27,\n> + HV_ARM64_REGISTER_X28,\n> + HV_ARM64_REGISTER_FP,\n> + HV_ARM64_REGISTER_LR,\n> + HV_ARM64_REGISTER_PC,\n\nWhy are you placing PC at name[31], given that you have to special case it everywhere else \nbelow?\n\n> +static int set_standard_regs(const CPUState *cpu)\n> +{\n> + size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);\n> + struct hv_register_assoc *assocs;\n> + int ret;\n> + ARMCPU *arm_cpu = ARM_CPU(cpu);\n> + CPUARMState *env = &arm_cpu->env;\n> +\n> + assocs = g_new0(hv_register_assoc, n_regs);\n\nThis is small enough to allocate in the local stack frame.\nSame for get_standard_regs.\n\n> +static void populate_standard_regs(const hv_register_assoc *assocs,\n> + CPUARMState *env)\n> +{\n> + size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);\n> +\n> + for (size_t i = 0; i < n_regs - 1; i++) {\n> + env->xregs[i] = assocs[i].value.reg64;\n> + }\n> +\n> + /* Last register is the program counter */\n> + env->pc = assocs[n_regs - 1].value.reg64;\n> +}\n\nWhy is this separate from get_standard_regs?\nYou don't have a similar split for set_standard_regs...\n\n> +int mshv_get_standard_regs(CPUState *cpu)\n\nI'll note that this isn't used outside of this file, and similarly for i386/mshv. It \ndoesn't need to be declared globally at all.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xVeyJSDw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1JVN3tsJz1yD5\n\tfor ; Thu, 23 Apr 2026 11:32:10 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFiue-0007Il-6c; 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