[{"id":3679697,"web_url":"http://patchwork.ozlabs.org/comment/3679697/","msgid":"<0E102AEB-7196-4968-B016-16879EF0D034@unpredictable.fr>","list_archive_url":null,"date":"2026-04-21T06:51:07","subject":"Re: [PATCH v3 10/14] target/arm: extract MMIO emulation logic for HVF\n & WHPX","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"content":"> On 21. Apr 2026, at 07:21, Aastha Rawat wrote:\n> \n> - Move common MMIO emulation code from HVF and WHPX backend to\n> arm_emulate_mmio() in helper.c.\n> - Update HVF and WHPX to use the new helper and shared types.\n\nHi,\n\nThis one is a bit interesting and not sure if it’s ok in this form.\n\nThat’s for one reason: it causes a slowdown on WHP and HVF by fetching\nstate (and sometimes setting) outside of their respective shared register pages.\n\nIn both of those APIs, the existence of the shared register page is opaque/hidden\naway, but if you aren’t careful about what you fetch you’re going to hit the slow\npath very easily.\n\nOn x86 WHPX, we have a state level abstraction with a FAST_RUNTIME_STATE\nthat only fetches a (sub)set accessible that is readable using only information\nfrom the shared register page - and that is supposed to be enough for the vast\nmajority of MMIO - that doesn’t touch the FP/MMX/SSE register files.\n\nAnd another possibility is putting it in a target/arm/emulate with mimicking\nthe x86_emul_ops interface with adding register callbacks to that so that state\nis fetched/set dynamically.\n\n\n> \n> Signed-off-by: Aastha Rawat \n> ---\n> target/arm/helper.c | 60 +++++++++++++++++++++++++++++++++++++++++++\n> target/arm/helper.h | 5 ++++\n> target/arm/hvf/hvf.c | 64 ++++++++++++++++++++++++----------------------\n> target/arm/syndrome.h | 37 +++++++++++++++++++++++++++\n> target/arm/whpx/whpx-all.c | 62 +++++++++++---------------------------------\n> 5 files changed, 150 insertions(+), 78 deletions(-)\n> \n> diff --git a/target/arm/helper.c b/target/arm/helper.c\n> index 7389f2988c..c9457c8384 100644\n> --- a/target/arm/helper.c\n> +++ b/target/arm/helper.c\n> @@ -34,6 +34,8 @@\n> #endif\n> #include \"cpregs.h\"\n> #include \"target/arm/gtimer.h\"\n> +#include \"target/arm/helper.h\"\n> +#include \"target/arm/syndrome.h\"\n> #include \"qemu/plugin.h\"\n> \n> static void switch_mode(CPUARMState *env, int mode);\n> @@ -9130,6 +9132,64 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)\n> take_aarch32_exception(env, new_mode, mask, offset, addr);\n> }\n> \n> +/*\n> + * Emulate a data abort syndrome for MMIO/guest memory access\n> + */\n> +int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa)\n> +{\n> + CPUARMState *env = &ARM_CPU(cpu)->env;\n> + int ret;\n> + IssDataAbort iss = { 0 };\n> + iss.raw = syndrome.iss;\n> +\n> + if (!(syndrome.ec == data_abort_lower || syndrome.ec == data_abort)) {\n> + error_report(\"Unknown exception class 0x%x\", syndrome.ec);\n> + return -1;\n> + }\n> +\n> + if (!iss.isv) {\n> + error_report(\"Cannot emulate MMIO. ISS not valid.\");\n> + return -1;\n> + }\n> +\n> + AddressSpace *as = cpu_get_address_space(cpu, ARMASIdx_NS);\n> + uint64_t len = 1ULL << iss.sas;\n> + bool sign_extend = iss.sse;\n> + uint64_t reg_index = iss.srt;\n> +\n> + if (iss.wnr) {\n> + uint8_t data[8];\n> + uint64_t val = reg_index < 31 ? env->xregs[reg_index] : 0ULL;\n> + val = cpu_to_le64(val);\n> + memcpy(data, &val, sizeof(val));\n> + ret = address_space_write(as, gpa, MEMTXATTRS_UNSPECIFIED, data, len);\n> + if (ret != MEMTX_OK) {\n> + error_report(\"Failed to write guest memory\");\n> + return -1;\n> + }\n> + } else {\n> + uint8_t data[8] = { 0 };\n> + ret = address_space_read(as, gpa, MEMTXATTRS_UNSPECIFIED, data, len);\n> + if (ret != MEMTX_OK) {\n> + error_report(\"Failed to read guest memory\");\n> + return -1;\n> + }\n> + uint64_t val;\n> + memcpy(&val, data, sizeof(val));\n> + val = le64_to_cpu(val);\n> + if (sign_extend) {\n> + uint64_t shift = 64 - (len * 8);\n> + val = (((int64_t)val << shift) >> shift);\n> + }\n> + if (!iss.sf) {\n> + val &= 0xffffffff;\n> + }\n> + env->xregs[reg_index] = val;\n> + }\n> +\n> + return 0;\n> +}\n> +\n> static int aarch64_regnum(CPUARMState *env, int aarch32_reg)\n> {\n> /*\n> diff --git a/target/arm/helper.h b/target/arm/helper.h\n> index b1c26c180e..3bc22595fd 100644\n> --- a/target/arm/helper.h\n> +++ b/target/arm/helper.h\n> @@ -3,8 +3,13 @@\n> #ifndef HELPER__H\n> #define HELPER__H\n> \n> +#include \n> +#include \n> #include \"exec/helper-proto-common.h\"\n> #include \"exec/helper-gen-common.h\"\n> +#include \"target/arm/syndrome.h\"\n> +\n> +int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa);\n> \n> #define HELPER_H \"tcg/helper-defs.h\"\n> #include \"exec/helper-proto.h.inc\"\n> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\n> index 5fc8f6bbbd..9ecad6c222 100644\n> --- a/target/arm/hvf/hvf.c\n> +++ b/target/arm/hvf/hvf.c\n> @@ -13,6 +13,7 @@\n> #include \"qemu/error-report.h\"\n> #include \"qemu/log.h\"\n> \n> +#include \"syndrome.h\"\n> #include \"system/runstate.h\"\n> #include \"system/hvf.h\"\n> #include \"system/hvf_int.h\"\n> @@ -35,6 +36,7 @@\n> #include \"target/arm/multiprocessing.h\"\n> #include \"target/arm/gtimer.h\"\n> #include \"target/arm/trace.h\"\n> +#include \"target/arm/helper.h\"\n> #include \"trace.h\"\n> #include \"migration/vmstate.h\"\n> \n> @@ -2072,12 +2074,15 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n> {\n> CPUARMState *env = cpu_env(cpu);\n> ARMCPU *arm_cpu = env_archcpu(env);\n> - uint64_t syndrome = excp->syndrome;\n> - uint32_t ec = syn_get_ec(syndrome);\n> + uint64_t syndrome;\n> + uint32_t ec;\n> bool advance_pc = false;\n> hv_return_t r;\n> int ret = 0;\n> \n> + syndrome = excp->syndrome;\n> + ec = syn_get_ec(syndrome);\n> +\n> switch (ec) {\n> case EC_SOFTWARESTEP: {\n> ret = EXCP_DEBUG;\n> @@ -2123,29 +2128,22 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n> break;\n> }\n> case EC_DATAABORT: {\n> - bool isv = syndrome & ARM_EL_ISV;\n> - bool iswrite = (syndrome >> 6) & 1;\n> - bool s1ptw = (syndrome >> 7) & 1;\n> - bool sse = (syndrome >> 21) & 1;\n> - uint32_t sas = (syndrome >> 22) & 3;\n> - uint32_t len = 1 << sas;\n> - uint32_t srt = (syndrome >> 16) & 0x1f;\n> - uint32_t cm = (syndrome >> 8) & 0x1;\n> - uint64_t val = 0;\n> + EsrEl2 esr_el2 = { .raw = syndrome };\n> + IssDataAbort iss = { .raw = esr_el2.iss };\n> uint64_t ipa = excp->physical_address;\n> AddressSpace *as = cpu_get_address_space(cpu, ARMASIdx_NS);\n> \n> - trace_hvf_data_abort(excp->virtual_address, ipa, isv,\n> - iswrite, s1ptw, len, srt);\n> + trace_hvf_data_abort(excp->virtual_address, ipa, iss.isv,\n> + iss.wnr, iss.s1ptw, 1ULL << iss.sas, iss.srt);\n> \n> - if (cm) {\n> + if (iss.cm) {\n> /* We don't cache MMIO regions */\n> advance_pc = true;\n> break;\n> }\n> \n> /* Handle dirty page logging for ram. */\n> - if (iswrite) {\n> + if (iss.wnr) {\n> hwaddr xlat;\n> MemoryRegion *mr = address_space_translate(as, ipa, &xlat,\n> NULL, true,\n> @@ -2172,27 +2170,31 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n> * TODO: If s1ptw, this is an error in the guest os page tables.\n> * Inject the exception into the guest.\n> */\n> - assert(!s1ptw);\n> -\n> - /*\n> - * TODO: ISV will be 0 for SIMD or SVE accesses.\n> - * Inject the exception into the guest.\n> - */\n> - assert(isv);\n> + assert(!iss.s1ptw);\n> \n> /*\n> * Emulate MMIO.\n> * TODO: Inject faults for errors.\n> */\n> - if (iswrite) {\n> - val = hvf_get_reg(cpu, srt);\n> - address_space_write(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len);\n> - } else {\n> - address_space_read(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len);\n> - if (sse) {\n> - val = sextract64(val, 0, len * 8);\n> - }\n> - hvf_set_reg(cpu, srt, val);\n> + ret = hvf_arch_get_registers(cpu);\n> + if (ret < 0) {\n> + error_report(\"Failed to get registers for MMIO\");\n> + esr_el2.raw, ipa);\n> + return -1;\n> + }\n> +\n> + ret = arm_emulate_mmio(cpu, esr_el2, ipa);\n> + if (ret < 0) {\n> + error_report(\"Failed to emulate MMIO, syndrome=0x%llx, gpa=0x%llx\",\n> + esr_el2.raw, ipa);\n> + return -1;\n> + }\n> +\n> + ret = hvf_arch_put_registers(cpu);\n> + if (ret < 0) {\n> + error_report(\"Failed to set registers after MMIO emulation\");\n> + esr_el2.raw, ipa);\n> + return -1;\n> }\n> advance_pc = true;\n> break;\n> diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\n> index bff61f052c..777d4fb975 100644\n> --- a/target/arm/syndrome.h\n> +++ b/target/arm/syndrome.h\n> @@ -101,6 +101,43 @@ typedef enum {\n> GCS_IT_GCSPOPX = 9,\n> } GCSInstructionType;\n> \n> +typedef union {\n> + uint64_t raw;\n> + struct {\n> + uint32_t iss:25;\n> + uint32_t il:1;\n> + uint32_t ec:6;\n> + uint32_t iss2:5;\n> + uint32_t _rsvd:27;\n> + } QEMU_PACKED;\n> +} EsrEl2;\n> +\n> +typedef union {\n> + uint32_t raw;\n> + struct {\n> + uint32_t dfsc:6;\n> + uint32_t wnr:1;\n> + uint32_t s1ptw:1;\n> + uint32_t cm:1;\n> + uint32_t ea:1;\n> + uint32_t fnv:1;\n> + uint32_t set:2;\n> + uint32_t vncr:1;\n> + uint32_t ar:1;\n> + uint32_t sf:1;\n> + uint32_t srt:5;\n> + uint32_t sse:1;\n> + uint32_t sas:2;\n> + uint32_t isv:1;\n> + uint32_t _unused:7;\n> + } QEMU_PACKED;\n> +} IssDataAbort;\n> +\n> +typedef enum {\n> + data_abort_lower = 36,\n> + data_abort = 37,\n> +} ExceptionClass;\n> +\n> #define ARM_EL_EC_LENGTH 6\n> #define ARM_EL_EC_SHIFT 26\n> #define ARM_EL_IL_SHIFT 25\n> diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c\n> index 513551bec1..b4daeaff4d 100644\n> --- a/target/arm/whpx/whpx-all.c\n> +++ b/target/arm/whpx/whpx-all.c\n> @@ -28,6 +28,8 @@\n> \n> #include \"syndrome.h\"\n> #include \"target/arm/cpregs.h\"\n> +#include \"target/arm/helper.h\"\n> +#include \"target/arm/syndrome.h\"\n> #include \"internals.h\"\n> \n> #include \"system/whpx-internal.h\"\n> @@ -330,59 +332,25 @@ static void whpx_set_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE val)\n> }\n> }\n> \n> -static uint64_t whpx_get_gp_reg(CPUState *cpu, int rt)\n> -{\n> - assert(rt <= 31);\n> - if (rt == 31) {\n> - return 0;\n> - }\n> - WHV_REGISTER_NAME reg = WHvArm64RegisterX0 + rt;\n> - WHV_REGISTER_VALUE val;\n> - whpx_get_reg(cpu, reg, &val);\n> -\n> - return val.Reg64;\n> -}\n> -\n> -static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val)\n> -{\n> - assert(rt < 31);\n> - WHV_REGISTER_NAME reg = WHvArm64RegisterX0 + rt;\n> - WHV_REGISTER_VALUE reg_val = {.Reg64 = val};\n> -\n> - whpx_set_reg(cpu, reg, reg_val);\n> -}\n> -\n> static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)\n> {\n> - uint64_t syndrome = ctx->Syndrome;\n> -\n> - bool isv = syndrome & ARM_EL_ISV;\n> - bool iswrite = (syndrome >> 6) & 1;\n> - bool sse = (syndrome >> 21) & 1;\n> - uint32_t sas = (syndrome >> 22) & 3;\n> - uint32_t len = 1 << sas;\n> - uint32_t srt = (syndrome >> 16) & 0x1f;\n> - uint32_t cm = (syndrome >> 8) & 0x1;\n> - uint64_t val = 0;\n> + int ret = 0;\n> + EsrEl2 esr = { .raw = ctx->Syndrome };\n> + uint32_t cm = (esr.iss >> 8) & 0x1;\n> \n> assert(!cm);\n> - assert(isv);\n> -\n> - if (iswrite) {\n> - val = whpx_get_gp_reg(cpu, srt);\n> - address_space_write(&address_space_memory,\n> - ctx->Gpa,\n> - MEMTXATTRS_UNSPECIFIED, &val, len);\n> - } else {\n> - address_space_read(&address_space_memory,\n> - ctx->Gpa,\n> - MEMTXATTRS_UNSPECIFIED, &val, len);\n> - if (sse) {\n> - val = sextract64(val, 0, len * 8);\n> - }\n> - whpx_set_gp_reg(cpu, srt, val);\n> +\n> + whpx_get_registers(cpu, WHPX_LEVEL_RUNTIME_STATE);\n> +\n> + ret = arm_emulate_mmio(cpu, esr, ctx->Gpa);\n> + if (ret < 0) {\n> + error_report(\"WHPX: Failed to handle MMIO, syndrome=0x%llx, gpa=0x%llx\",\n> + esr.raw, ctx->Gpa);\n> + return -1;\n> }\n> \n> + whpx_set_registers(cpu, WHPX_LEVEL_RUNTIME_STATE);\n> +\n> return 0;\n> }\n> \n> \n> -- \n> 2.45.4\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=PYPOqDmh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0Chv6BMwz1yGt\n\tfor ; Tue, 21 Apr 2026 16:52:30 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF4xJ-0003WZ-0R; Tue, 21 Apr 2026 02:51:33 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF4xG-0003Vy-A9\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 02:51:30 -0400","from ci-2001e-snip4-2.eps.apple.com ([57.103.91.35]\n helo=outbound.ci.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF4xD-0008Ob-Ky\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 02:51:30 -0400","from outbound.ci.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-central-1k-100-percent-4 (Postfix) with ESMTPS id\n 2D3C11800181; Tue, 21 Apr 2026 06:51:21 +0000 (UTC)","from smtpclient.apple (unknown [17.57.156.36])\n by p00-icloudmta-asmtp-us-central-1k-100-percent-4 (Postfix) with ESMTPSA id\n 947F9180012F; Tue, 21 Apr 2026 06:51:19 +0000 (UTC)"],"X-ICL-Out-Info":"\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJB01fDl4fBBdGGVUERx5dVlAEGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVIdlwHWXM1e1UEXA5dH0QATgtAdVsDRhRJBVUAUnc2CTwDXgMrRx5JClYJXghGEVsUVkNRGQxQTQFDCAoIRwNNF14yUwRfEVAW","Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776754285; x=1779346285;\n bh=3XthME9dBU3g1tLdThMwSV0+O7ZUauHCiKnoTwCOISI=;\n h=Content-Type:Mime-Version:Subject:From:Date:Message-Id:To:x-icloud-hme;\n b=PYPOqDmhfigFVz3jdh/mUzH2dMM1Zl5YRDj/RaGiBxntfeAvfVdra/2U9QnqQvyAZ+AABfTmKP23a9y+l9Plby2GEIbXmnh+upyab249ILEO5oKLH/srg8iv1Zr+9VCX0dZjd6S30YXOBZQro3EoJsqkiPROoqbjHtfHB/ziK3ZkF8qo5nByKiSNzmKmZNkJKIH2sc6n2ajAR8fw3SYRRScwZYmu8Iy9iQIf8f39aZOnG08Z6PJfEeTKZoHJvil5m8k19tDWBLSHaQbAVJITIW72jO7lA5DL0/2GHM2NQq5z6h9ViMwoLkJzk66NLKOvd3tUIRHDxI6r3IGzZyBQ+g==","mail-alias-created-date":"1752046281608","Content-Type":"text/plain;\n\tcharset=utf-8","Mime-Version":"1.0 (Mac OS X Mail 16.0 \\(3864.500.181\\))","Subject":"Re: [PATCH v3 10/14] target/arm: extract MMIO emulation logic for HVF\n & WHPX","From":"Mohamed Mediouni ","In-Reply-To":"\n <20260421-mshv_accel_arm64_supp-v3-10-469f544778ba@linux.microsoft.com>","Date":"Tue, 21 Apr 2026 08:51:07 +0200","Cc":"qemu-devel@nongnu.org, Magnus Kulke ,\n Wei Liu , Paolo Bonzini ,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= ,\n\t=?utf-8?b?IkRhbmllbCBQLiBCZXJyYW5nw6ki?= , =?utf-8?q?P?=\n\t=?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= ,\n Peter Maydell ,\n Anirudh Rayabharam ,\n Magnus Kulke , qemu-arm@nongnu.org,\n Alexander Graf , Pedro Barbuda ","Content-Transfer-Encoding":"quoted-printable","Message-Id":"<0E102AEB-7196-4968-B016-16879EF0D034@unpredictable.fr>","References":"\n <20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com>\n <20260421-mshv_accel_arm64_supp-v3-10-469f544778ba@linux.microsoft.com>","To":"Aastha Rawat ","X-Mailer":"Apple Mail (2.3864.500.181)","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIxMDA2NSBTYWx0ZWRfX0k4yYwFCzll4\n hepL60nEQpkz9G1Y5f6f83CW5e7KhQRnEww65h7nEf/sqLOd7Ido/tvMqdz/UDVoobYDekDIoal\n mO5NHvasM/3fiU0saB2Zbc6Mi0TdrOCN/uT+P6nUKhIzTTeuVc3No/pP2jXtPjoqblF9gXUr9kN\n 3//jfvULfTMeEMT93PlCVPKreecYe1M7aVgF76EKUt8fqDwV/M4SHl98brtMkjkg4NxCiZsWwbA\n QHLYnwMYqbyK1Y9t5Hi1KSREuUsF5QnZhPL/r9SjRfBSOTEtTh0bJB6OqI6yzGk+3RSz6DC14fL\n RZVn+MMEZF7K56cWL8z/m2udjaaPsYpyUE2DrpgOr3LrmtEAOZKKTFeRZONl9c=","X-Proofpoint-GUID":"Zoaeis1s--mCtOigi7GPAo_LV13P3CyK","X-Authority-Info-Out":"v=2.4 cv=LuGfC3dc c=1 sm=1 tr=0 ts=69e71e6c\n cx=c_apl:c_pps:t_out a=2G65uMN5HjSv0sBfM2Yj2w==:117\n a=2G65uMN5HjSv0sBfM2Yj2w==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=yMhMjlubAAAA:8 a=dJ-s-Lo7nvDzl-0enaAA:9\n a=QEXdDO2ut3YA:10","X-Proofpoint-ORIG-GUID":"Zoaeis1s--mCtOigi7GPAo_LV13P3CyK","Received-SPF":"pass client-ip=57.103.91.35;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.ci.icloud.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]