[{"id":3681169,"web_url":"http://patchwork.ozlabs.org/comment/3681169/","msgid":"","list_archive_url":null,"date":"2026-04-22T19:18:55","subject":"Re: [PATCH v3] match.pd: simplify lshift const cmp using bit_and\n [PR124019]","submitter":{"id":92288,"url":"http://patchwork.ozlabs.org/api/people/92288/","name":"Daniel Barboza","email":"daniel.barboza@oss.qualcomm.com"},"content":"On 4/20/2026 3:02 PM, Daniel Henrique Barboza wrote:\n> From: Daniel Barboza \n> \n> Given a comparison with the format\n> \n> A << CST1 EQ|NE CST2\n> \n> Turn it into:\n> \n> A & CSTmask EQ|NE CST2 >> CST1\n\nSo I was looking at a potential RISC-V test regression that would be related\nto this patch (ps: it isn't) and then I noticed that the RISC-V code being\ngenerated got worse with this patch.\n\nConsider this test:\n\n_Bool f1(long a)\n{\n long b = a << 4;\n return b == -128;\n}\n\nGenerated RISC-V code from trunk:\n\nf1:\n.LFB0:\n .cfi_startproc\n slli a0,a0,4 # 6 [c=4 l=4] ashldi3\n addi a0,a0,128 # 7 [c=4 l=4] *adddi3/1\n seqz a0,a0 # 16 [c=4 l=4] *seq_zero_didi\n ret\n\n\nIn https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124019 Jeff suggested that a better\ncode would be to use \"andi\" to mask the bits before doing the comparison. But after\nthis patch this is the RISC-V code being generated:\n\nf1:\n.LFB0:\n .cfi_startproc\n slli a0,a0,4 # 6 [c=4 l=4] ashldi3\n bseti a5,zero,60 # 32 [c=4 l=4] *movdi_64bit/1\n addi a5,a5,-8 # 33 [c=4 l=4] *adddi3/1\n srli a0,a0,4 # 7 [c=4 l=4] lshrdi3\n sub a0,a0,a5 # 10 [c=4 l=4] subdi3\n seqz a0,a0 # 19 [c=4 l=4] *seq_zero_didi\n ret # 36 [c=0 l=4] simple_return\n .cfi_endproc\n\n\nThe reason is that \"andi\" uses a 12 bit immediate, and with this patch we're turning\nthat into\n\n # RANGE [irange] long int [0, 1152921504606846975] MASK 0xfffffffffffffff VALUE 0x0\n _4 = a_1(D) & 1152921504606846975;\n _2 = _4 == 1152921504606846968;\n # VUSE <.MEM_3(D)>\n return _2\n\nAnd this immediate can't fit a regular 'andi'.\n\nIn fact, if you change the code to generate a smaller immediate:\n\n_Bool f2(char a)\n{\n char b = a << 4;\n return b == 16;\n}\n\nThe intended code with 'andi' will show:\n\nf2:\n.LFB1:\n .cfi_startproc\n andi a0,a0,15 # 8 [c=4 l=4] *anddi3/1\n addi a0,a0,-1 # 10 [c=4 l=4] *adddi3/1\n seqz a0,a0 # 19 [c=4 l=4] *seq_zero_didi\n ret # 32 [c=0 l=4] simple_return\n\n\nGiven that this is a RISC-V bug it's not ideal that RISC-V is taking a hit for this\nchange. We can't add target specific logic in Gimple (check if the immediate fits\nin 12 bits) so one option is a RISC-V backend patch. At any rate it seems like this\ngeneric approach won't work.\n\n\nJeff, for now please remove this patch from any test queue you might have.\n\n\nThanks,\nDaniel\n\n\n> \n> Where 'CSTmask' is a bitmask that filters A bits that would be discarded\n> during the shift. The idea is that a bit_and is, on most common targets\n> at least, more efficient than a lshift.\n> \n> Bootstrapped and regression tested on x86, aarch64 and RISC-V.\n> \n> \tPR tree-optimization/124019\n> \n> gcc/ChangeLog:\n> \n> \t* match.pd (`A< (A&CSTmask) EQ|NE (CST2>>CST1)`):\n> \tNew pattern.\n> \n> gcc/testsuite/ChangeLog:\n> \n> \t* gcc.target/aarch64/cmp_shifted_reg_1.c: changed comparison\n> \tto \">\" to dodge this optimization and keep generating the\n> \texpected shift compare insn.\n> \t* gcc.dg/tree-ssa/pr124019.c: New test.\n> ---\n> \n> Changes from v2:\n> - Wrapped the pattern around #if GIMPLE;\n> - Added check for lshift single_use();\n> - negs.c changes were reverted. The pattern is now checking\n> for lshift single_use() and the test is no longer being affected;\n> - Removed the \"A << 1 != CST1\" check related to pr114760-1.c and\n> the CLZ builtin. Checking for single_use() is enough to avoid\n> tripping on the builtin, thus we're free to support this use\n> case;\n> - Added check for CST2 zero bits.\n> - v2 link: https://gcc.gnu.org/pipermail/gcc-patches/2026-March/709651.html\n> \n> gcc/match.pd | 36 +++++++++++++++++\n> gcc/testsuite/gcc.dg/tree-ssa/pr124019.c | 40 +++++++++++++++++++\n> .../gcc.target/aarch64/cmp_shifted_reg_1.c | 2 +-\n> 3 files changed, 77 insertions(+), 1 deletion(-)\n> create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr124019.c\n> \n> diff --git a/gcc/match.pd b/gcc/match.pd\n> index 7b652afb43d..d34d3ddf35f 100644\n> --- a/gcc/match.pd\n> +++ b/gcc/match.pd\n> @@ -1454,6 +1454,42 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)\n> (if (TYPE_UNSIGNED (type))\n> (bit_and @0 (bit_not (lshift { build_all_ones_cst (type); } @1)))))\n> \n> +#if GIMPLE\n> +/* PR124019: A << CST1 EQ|NE CST2 -> (A & CSTmask) EQ|NE (CST2 >> CST1); */\n> +(for cmp (eq ne)\n> + (simplify\n> + (cmp (lshift@3 @0 INTEGER_CST@1) INTEGER_CST@2)\n> + (if (INTEGRAL_TYPE_P (TREE_TYPE (@0))\n> +\t&& single_use (@3)\n> +\t&& tree_fits_uhwi_p (@1)\n> +\t&& tree_to_uhwi (@1) < TYPE_PRECISION (TREE_TYPE (@0))\n> +\t&& tree_to_uhwi (@1) < TYPE_PRECISION (TREE_TYPE (@2)))\n> + (with {\n> + unsigned prec2 = TYPE_PRECISION (TREE_TYPE (@2));\n> + wide_int cst2_mask = wi::mask (tree_to_uhwi (@1), false, prec2);\n> + }\n> + /* We need to assert that CST2 lower CST1 bits are zero for the\n> +\ttransformation to be valid. This seem to be already taken\n> +\tcare of\tby CCP, turning cases like \"a << 4 == 17\" into\n> +\t\"return 0\", and this check might be redundant. We can't rely\n> +\ton CCP always having our backs though, therefore validate the\n> +\tzero bits here to be sure. */\n> + (if (wi::to_wide (@2) == 0\n> +\t || wi::eq_p (wi::bit_and (cst2_mask, wi::to_wide (@2)),\n> +\t\t wi::zero (prec2)))\n> + (with {\n> +\tunsigned prec = TYPE_PRECISION (TREE_TYPE (@0));\n> +\tunsigned mask_len = prec - tree_to_uhwi (@1);\n> +\ttree cst1_mask = wide_int_to_tree (TREE_TYPE (@0),\n> +\t\t\t\t\t wi::mask (mask_len, false, prec));\n> +\ttree type3 = TREE_TYPE (@3);\n> +\twide_int lrshift = wi::lrshift (wi::to_wide (@2), wi::to_wide (@1));\n> +\ttree cst_lrshift = wide_int_to_tree (type3, lrshift);\n> + }\n> + (cmp (convert:type3 (bit_and @0 { cst1_mask; }))\n> +\t { cst_lrshift; })))))))\n> +#endif\n> +\n> (for bitop (bit_and bit_ior)\n> cmp (eq ne)\n> /* PR35691: Transform\n> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr124019.c b/gcc/testsuite/gcc.dg/tree-ssa/pr124019.c\n> new file mode 100644\n> index 00000000000..bd46864c75b\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr124019.c\n> @@ -0,0 +1,40 @@\n> +/* { dg-additional-options -O2 } */\n> +/* { dg-additional-options -fdump-tree-optimized } */\n> +\n> +typedef unsigned char uint8_t;\n> +typedef signed char int8_t;\n> +\n> +uint8_t f1(int8_t a)\n> +{\n> + int8_t b = a << 4;\n> + return b == -128;\n> +}\n> +\n> +uint8_t f2(int8_t a)\n> +{\n> + int8_t b = a << 4;\n> + return b != -128;\n> +}\n> +\n> +uint8_t f3(int8_t a)\n> +{\n> + int8_t b = a << 6;\n> + return b == -128;\n> +}\n> +\n> +uint8_t f4(int8_t a)\n> +{\n> + int8_t b = a << 7;\n> + return b == -128;\n> +}\n> +\n> +uint8_t f5(int8_t a)\n> +{\n> + int8_t b = a << 1;\n> + return b == -128;\n> +}\n> +/* { dg-final { scan-tree-dump-times \" & 15;\" 2 optimized } } */\n> +/* { dg-final { scan-tree-dump-times \" & 3;\" 1 optimized } } */\n> +/* { dg-final { scan-tree-dump-times \" & 1;\" 1 optimized } } */\n> +/* { dg-final { scan-tree-dump-times \" & 127;\" 1 optimized } } */\n> +/* { dg-final { scan-tree-dump-times \" << \" 0 optimized } } */\n> diff --git a/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c\n> index cacecf4e71d..8feedce5c51 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c\n> @@ -4,7 +4,7 @@\n> int f3 (int x, int y)\n> {\n> int res = x << 3;\n> - return res != 0;\n> + return res > 0;\n> }\n> \n> /* We should combine the shift and compare */","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=K4KamZlW;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Oad0rAEx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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