[{"id":3679503,"web_url":"http://patchwork.ozlabs.org/comment/3679503/","msgid":"","list_archive_url":null,"date":"2026-04-20T17:52:31","subject":"RE: [PATCH v5 6/9] pwm: rzg2l-gpt: Add prescale_mult variable to\n struct rzg2l_gpt_info","submitter":{"id":79631,"url":"http://patchwork.ozlabs.org/api/people/79631/","name":"Biju Das","email":"biju.das.jz@bp.renesas.com"},"content":"Hi,\n\n> -----Original Message-----\n> From: Biju \n> Sent: 20 April 2026 11:43\n> Subject: [PATCH v5 6/9] pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info\n> \n> From: Biju Das \n> \n> RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4.\n> Add prescale_mult variable to struct rzg2l_gpt_info for handling this difference.\n> \n> Reviewed-by: Tommaso Merciai \n> Signed-off-by: Biju Das \n> ---\n> v4->v5:\n> * No change.\n> v3->v4:\n> * Updated commit header and description\n> * Renamed prescale_pow_of_two_mult_factor->prescale_mult\n> v2->v3:\n> * No change.\n> v1->v2:\n> * Collected tag.\n> ---\n> drivers/pwm/pwm-rzg2l-gpt.c | 19 +++++++++++++------\n> 1 file changed, 13 insertions(+), 6 deletions(-)\n> \n> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index af594c1ce536..4324ffc8629d\n> 100644\n> --- a/drivers/pwm/pwm-rzg2l-gpt.c\n> +++ b/drivers/pwm/pwm-rzg2l-gpt.c\n> @@ -92,6 +92,7 @@\n> \n> struct rzg2l_gpt_info {\n> \tu32 gtcr_tpcs;\n> +\tu8 prescale_mult;\n> };\n> \n> struct rzg2l_gpt_chip {\n> @@ -234,6 +235,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt, static u64\n> rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,\n> \t\t\t\t\t u32 val, u8 prescale)\n> {\n> +\tconst struct rzg2l_gpt_info *info = rzg2l_gpt->info;\n> \tu64 tmp;\n> \n> \t/*\n> @@ -243,15 +245,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,\n> \t * < 2^32 * 2^10 * 2^20\n> \t * = 2^62\n> \t */\n> -\ttmp = (u64)val << (2 * prescale);\n> +\ttmp = (u64)val << (info->prescale_mult * prescale);\n> \ttmp *= USEC_PER_SEC;\n> \n> \treturn DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); }\n> \n> -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)\n> +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info,\n> +\t\t\t\t\tu64 period_or_duty_cycle, u8 prescale)\n> {\n> -\treturn min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),\n> +\treturn min_t(u64,\n> +\t\t DIV_ROUND_DOWN_ULL(period_or_duty_cycle,\n> +\t\t\t\t\t1 << (info->prescale_mult * prescale)),\n> \t\t U32_MAX);\n> }\n> \n> @@ -262,6 +267,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,\n> \n> {\n> \tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n> +\tconst struct rzg2l_gpt_info *info = rzg2l_gpt->info;\n> \tstruct rzg2l_gpt_waveform *wfhw = _wfhw;\n> \tbool is_small_second_period = false;\n> \tu8 ch = RZG2L_GET_CH(pwm->hwpwm);\n> @@ -299,8 +305,8 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,\n> \t\t}\n> \t}\n> \n> -\twfhw->prescale = rzg2l_gpt_calculate_prescale(period_ticks);\n> -\tpv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);\n> +\twfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);\n\nThis is wrong here, as I dropped rzg2l_gpt in patch #3.\n\n\nCheers,\nBiju","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=bp.renesas.com header.i=@bp.renesas.com\n header.a=rsa-sha256 header.s=selector1 header.b=UJ2EQzr3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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