[{"id":3679216,"web_url":"http://patchwork.ozlabs.org/comment/3679216/","msgid":"","list_archive_url":null,"date":"2026-04-20T04:32:10","subject":"Re: [PATCH v1] mach-snapdragon: Add KVM hypervisor support","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"Hi Aswin,\n\nOn 2026-04-19T17:38:29, Aswin Murugan wrote:\n> mach-snapdragon: Add KVM hypervisor support\n>\n> Enable Linux KVM virtualization on Snapdragon SoCs.\n>\n> Introduce CONFIG_QCOM_KVM_SUPPORT to select KVM or Gunyah\n> hypervisor modes at build time.\n>\n> qcom-priv.h:\n> - Add TrustZone SMC interface definitions and parameter IDs\n> - Define hypervisor boot types (GUNYAH=0, KVM=1)\n> - Add TCR_EL2 bit field definitions for memory config\n>\n> board.c:\n> - Add qcom_configure_kvm_hypervisor() with EL-aware logic\n> - EL2: Perform direct SMC call for hypervisor setup\n> - EL1: Save context, disable caches, run SMC, restore state,\n> reconfigure TCR_EL2, re-enable caches\n> - Add qcom_configure_gunyah_hypervisor() for standard flow\n> - Add SCM service availability checks\n>\n> [...]\n>\n> arch/arm/mach-snapdragon/Kconfig | 7 ++\n> arch/arm/mach-snapdragon/board.c | 154 +++++++++++++++++++++++++++++++++++\n> arch/arm/mach-snapdragon/qcom-priv.h | 31 +++++++\n> 3 files changed, 192 insertions(+)\n\n> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\n> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)\n> + log_debug(\"At EL1, saving register context\\n\");\n> +\n> + u64 ttbr0_el1, tcr_el1, tcr_el2, mair_el1;\n> + u64 t0sz, phys_addr_size;\n\nPlease can you move these declarations to the top of the function\nalongside res and current_el.\n\n> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\n> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)\n> + if (current_el != 2) {\n> + log_debug(\"No EL2 transition, skipping TCR_EL2 config\\n\");\n> + icache_enable();\n> + dcache_enable();\n> + log_warning(\"KVM hypervisor configuration failed\\n\");\n> + return 0;\n> + }\n\nThis logs a warning saying configuration failed but returns 0\n(success). If the EL2 transition truly failed, shouldn't it an error?\nIf it is intentionally a soft failure, the log message should clarify\nwhy.\n\n> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\n> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)\n> + arm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,\n> + TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,\n> + TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> + 0, 0, 0, 0, 0, &res);\n> +\n> + if (res.a0 != 0)\n> + log_debug(\"KVM milestone service not available (0x%lx)\\n\", res.a0);\n\nJust to check: if the service is not available, should the function\ncontinue anyway? In qcom_configure_gunyah_hypervisor() you return\nearly when the service check fails, but here you continue regardless.\nA brief comment explaining why would help.\n\n> diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h\n> @@ -17,6 +17,37 @@ extern enum qcom_boot_source qcom_boot_source;\n> +/* TCR_EL2 bit field definitions */\n> +#define TCR_T0SZ_MASK 0x1FUL\n> +#define TCR_PS_MASK (0x7UL << 32)\n> +#define TCR_PS_SHIFT 16\n> +#define TCR_SH_ORGN_IRGN_MASK 0x3F00UL\n> +#define TCR_SH_INNER_SHAREABLE (3UL << 12)\n> +#define TCR_ORGN_WRITE_BACK_ALLOC BIT(10)\n> +#define TCR_IRGN_WRITE_BACK_ALLOC BIT(8)\n\narch/arm/include/asm/armv8/mmu.h already defines TCR_IRGN_WBWA,\nTCR_ORGN_WBWA, and TCR_SHARED_INNER with the same values. Please can\nyou reuse those existing definitions rather than duplicating them\nhere.\n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256\n header.s=google header.b=CYAYhCTt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org\n header.b=\"CYAYhCTt\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=sjg@chromium.org"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzXdm4kmlz1yGs\n\tfor ; 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Sun, 19 Apr 2026\n 21:32:23 -0700 (PDT)","MIME-Version":"1.0","References":"<20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com>","In-Reply-To":"<20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com>","From":"Simon Glass ","Date":"Mon, 20 Apr 2026 16:32:10 +1200","X-Gm-Features":"AQROBzDY59pCEWUrP8PCT3Pxm1C34OT88gwFPvGdhL8gX7-nbBgkXru1TrxM41E","Message-ID":"\n ","Subject":"Re: [PATCH v1] mach-snapdragon: Add KVM hypervisor support","To":"aswin.murugan@oss.qualcomm.com","Cc":"trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sughosh.ganu@arm.com, gchan9527@gmail.com,\n u-boot-qcom@groups.io, u-boot@lists.denx.de","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3679274,"web_url":"http://patchwork.ozlabs.org/comment/3679274/","msgid":"<7ee17361-2edc-42ab-a56d-20167f3bd02b@linaro.org>","list_archive_url":null,"date":"2026-04-20T07:50:36","subject":"Re: [PATCH v1] mach-snapdragon: Add KVM hypervisor support","submitter":{"id":84903,"url":"http://patchwork.ozlabs.org/api/people/84903/","name":"Neil Armstrong","email":"neil.armstrong@linaro.org"},"content":"Hi,\n\nOn 4/19/26 19:38, Aswin Murugan wrote:\n> Enable Linux KVM virtualization on Snapdragon SoCs.\n> \n> Introduce CONFIG_QCOM_KVM_SUPPORT to select KVM or Gunyah\n> hypervisor modes at build time.\n\nPlease stop using KVW when disabling Gunyah, KVM is a possible hypervisor when running EL2,\nbut is completely optional. I know internally you refer to KVM when not using Gunyah,\nbut this make 0 sense at all to user this term when writing patches on the mailing-list.\n\nJust rewrite like this: add support for disabling Gunyah or add support for booting into EL2\n\n> \n> qcom-priv.h:\n> - Add TrustZone SMC interface definitions and parameter IDs\n> - Define hypervisor boot types (GUNYAH=0, KVM=1)\n> - Add TCR_EL2 bit field definitions for memory config\n> \n> board.c:\n> - Add qcom_configure_kvm_hypervisor() with EL-aware logic\n> - EL2: Perform direct SMC call for hypervisor setup\n> - EL1: Save context, disable caches, run SMC, restore state,\n> reconfigure TCR_EL2, re-enable caches\n> - Add qcom_configure_gunyah_hypervisor() for standard flow\n> - Add SCM service availability checks\n\nNo need to to a summary of the patch, if it changes to much stuff (which seems to be the case here)\njust split it into multiple small changes, and explain WHY instead of WHAT in the commit message.\n\n> \n> Default mode remains Gunyah. Enable CONFIG_QCOM_KVM_SUPPORT to\n> select KVM for Linux.\n\nNeil\n\n> \n> Signed-off-by: Aswin Murugan \n> ---\n> arch/arm/mach-snapdragon/Kconfig | 7 ++\n> arch/arm/mach-snapdragon/board.c | 154 +++++++++++++++++++++++++++\n> arch/arm/mach-snapdragon/qcom-priv.h | 31 ++++++\n> 3 files changed, 192 insertions(+)\n> \n> diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig\n> index d3de8693b5a..2e5676945ca 100644\n> --- a/arch/arm/mach-snapdragon/Kconfig\n> +++ b/arch/arm/mach-snapdragon/Kconfig\n> @@ -42,4 +42,11 @@ config SYS_CONFIG_NAME\n> \t Based on this option include/configs/.h header\n> \t will be used for board configuration.\n> \n> +config QCOM_KVM_SUPPORT\n> +\tbool \"Enable KVM support for Qualcomm platforms\"\n> +\tdepends on ARM64\n> +\thelp\n> +\t This configures the hypervisor interface during boot to support\n> +\t KVM virtualization instead of the default Gunyah hypervisor.\n> +\n> endif\n> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\n> index 5fb3240acc5..2926dd8ccc0 100644\n> --- a/arch/arm/mach-snapdragon/board.c\n> +++ b/arch/arm/mach-snapdragon/board.c\n> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)\n> {\n> }\n> \n> +/**\n> + * qcom_configure_kvm_hypervisor() - Configure hypervisor for KVM guest mode\n> + *\n> + * Configures the hypervisor for KVM operation:\n> + * - EL2 path: Direct SMC call\n> + * - EL1 path: Save context, disable caches, SMC call, restore context\n> + *\n> + * Return: 0 on success, negative error code on failure\n> + */\n> +static int qcom_configure_kvm_hypervisor(void)\n> +{\n> +\tstruct arm_smccc_res res;\n> +\tu64 current_el;\n> +\n> +\tasm volatile(\"mrs %0, CurrentEL\" : \"=r\" (current_el));\n> +\tcurrent_el = (current_el >> 2) & 0x3;\n> +\n> +\tlog_info(\"Configuring hypervisor for KVM (EL%llu)\\n\", current_el);\n> +\n> +\tarm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,\n> +\t\t TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t 0, 0, 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0)\n> +\t\tlog_debug(\"KVM milestone service not available (0x%lx)\\n\", res.a0);\n> +\n> +\tif (current_el == 2) {\n> +\t\tlog_debug(\"At EL2\\n\");\n> +\n> +\t\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n> +\t\t\t 0, 0, QCOM_HYP_BOOT_TYPE_KVM,\n> +\t\t\t 0, 0, 0, &res);\n> +\n> +\t\tif (res.a0 != 0) {\n> +\t\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n> +\t\t\treturn -EIO;\n> +\t\t}\n> +\n> +\t\tlog_info(\"KVM hypervisor configured\\n\");\n> +\t\treturn 0;\n> +\t}\n> +\n> +\tlog_debug(\"At EL1, saving register context\\n\");\n> +\n> +\tu64 ttbr0_el1, tcr_el1, tcr_el2, mair_el1;\n> +\tu64 t0sz, phys_addr_size;\n> +\n> +\t/* Save EL1 system register context */\n> +\tasm volatile(\"mrs %0, ttbr0_el1\" : \"=r\" (ttbr0_el1));\n> +\tasm volatile(\"mrs %0, tcr_el1\" : \"=r\" (tcr_el1));\n> +\tasm volatile(\"mrs %0, mair_el1\" : \"=r\" (mair_el1));\n> +\n> +\tt0sz = tcr_el1 & TCR_T0SZ_MASK;\n> +\tphys_addr_size = tcr_el1 & TCR_PS_MASK;\n> +\n> +\tlog_debug(\"Saved context: TTBR0=0x%llx TCR=0x%llx MAIR=0x%llx\\n\",\n> +\t\t ttbr0_el1, tcr_el1, mair_el1);\n> +\n> +\ticache_disable();\n> +\tdcache_disable();\n> +\n> +\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n> +\t\t 0, 0, QCOM_HYP_BOOT_TYPE_KVM,\n> +\t\t 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0) {\n> +\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n> +\t\ticache_enable();\n> +\t\tdcache_enable();\n> +\t\treturn -EIO;\n> +\t}\n> +\n> +\tasm volatile(\"mrs %0, CurrentEL\" : \"=r\" (current_el));\n> +\tcurrent_el = (current_el >> 2) & 0x3;\n> +\n> +\tasm volatile(\"msr ttbr0_el1, %0\" : : \"r\" (ttbr0_el1));\n> +\tasm volatile(\"isb\");\n> +\n> +\tif (current_el != 2) {\n> +\t\tlog_debug(\"No EL2 transition, skipping TCR_EL2 config\\n\");\n> +\t\ticache_enable();\n> +\t\tdcache_enable();\n> +\t\tlog_warning(\"KVM hypervisor configuration failed\\n\");\n> +\t\treturn 0;\n> +\t}\n> +\n> +\t/* Read current TCR_EL2 and reconfigure it */\n> +\tasm volatile(\"mrs %0, tcr_el2\" : \"=r\" (tcr_el2));\n> +\n> +\ttcr_el2 &= ~(TCR_T0SZ_MASK | (0x7UL << 16));\n> +\ttcr_el2 |= t0sz | (phys_addr_size >> TCR_PS_SHIFT);\n> +\n> +\ttcr_el2 &= ~TCR_SH_ORGN_IRGN_MASK;\n> +\ttcr_el2 |= TCR_SH_INNER_SHAREABLE |\n> +\t\t TCR_ORGN_WRITE_BACK_ALLOC |\n> +\t\t TCR_IRGN_WRITE_BACK_ALLOC;\n> +\n> +\tasm volatile(\"msr tcr_el2, %0\" : : \"r\" (tcr_el2));\n> +\tasm volatile(\"msr mair_el1, %0\" : : \"r\" (mair_el1));\n> +\tasm volatile(\"isb\");\n> +\n> +\ticache_enable();\n> +\tdcache_enable();\n> +\n> +\tlog_info(\"KVM hypervisor configured\\n\");\n> +\treturn 0;\n> +}\n> +\n> +/**\n> + * qcom_configure_gunyah_hypervisor() - Configure hypervisor for Gunyah mode\n> + *\n> + * Configures the hypervisor for standard Gunyah operation.\n> + *\n> + * Return: 0 on success, negative error code on failure\n> + */\n> +static int qcom_configure_gunyah_hypervisor(void)\n> +{\n> +\tstruct arm_smccc_res res;\n> +\n> +\tlog_info(\"Configuring hypervisor for Gunyah mode\\n\");\n> +\n> +\tarm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,\n> +\t\t TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t 0, 0, 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0) {\n> +\t\tlog_debug(\"Hypervisor milestone service not available (0x%lx)\\n\", res.a0);\n> +\t\treturn 0;\n> +\t}\n> +\n> +\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n> +\t\t 0, 0, QCOM_HYP_BOOT_TYPE_GUNYAH,\n> +\t\t 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0) {\n> +\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n> +\t\treturn -EIO;\n> +\t}\n> +\n> +\tlog_info(\"Gunyah hypervisor configured\\n\");\n> +\treturn 0;\n> +}\n> +\n> #define KERNEL_COMP_SIZE\tSZ_64M\n> arch/arm/mach-snapdragon/Kconfig #ifdef CONFIG_FASTBOOT_BUF_SIZE\n> #define FASTBOOT_BUF_SIZE CONFIG_FASTBOOT_BUF_SIZE\n> @@ -570,6 +718,12 @@ int board_late_init(void)\n> \tqcom_late_init();\n> \n> \tqcom_show_boot_source();\n> +\n> +\tif (IS_ENABLED(CONFIG_QCOM_KVM_SUPPORT))\n> +\t\tqcom_configure_kvm_hypervisor();\n> +\telse\n> +\t\tqcom_configure_gunyah_hypervisor();\n> +\n> \t/* Configure the dfu_string for capsule updates */\n> \tqcom_configure_capsule_updates();\n> \n> diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h\n> index b8bf574e8bb..a5d9dec6aa7 100644\n> --- a/arch/arm/mach-snapdragon/qcom-priv.h\n> +++ b/arch/arm/mach-snapdragon/qcom-priv.h\n> @@ -17,6 +17,37 @@ enum qcom_boot_source {\n> \n> extern enum qcom_boot_source qcom_boot_source;\n> \n> +/* TrustZone SMC definitions */\n> +#define TZ_SYSCALL_CREATE_SMC_ID(o, s, f) \\\n> +\t((u32)((((o) & 0x3f) << 24) | (((s) & 0xff) << 8) | ((f) & 0xff)))\n> +\n> +#define TZ_OWNER_SIP\t\t\t\t2\n> +#define TZ_SVC_BOOT\t\t\t\t1\n> +#define TZ_SVC_INFO\t\t\t\t6\n> +#define TZ_BOOT_CMD_KVM_MILESTONE\t\t0x21\n> +#define TZ_INFO_IS_SVC_AVAILABLE_CMD\t\t0x01\n> +\n> +#define TZ_CONFIGURE_MILESTONE_SERVICE_ID \\\n> +\tTZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_SIP, TZ_SVC_BOOT, TZ_BOOT_CMD_KVM_MILESTONE)\n> +#define TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID\t\t0x23\n> +\n> +#define TZ_INFO_IS_SVC_AVAILABLE_ID \\\n> +\tTZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_SIP, TZ_SVC_INFO, TZ_INFO_IS_SVC_AVAILABLE_CMD)\n> +#define TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID\t\t0x1\n> +\n> +/* Hypervisor boot types */\n> +#define QCOM_HYP_BOOT_TYPE_GUNYAH\t\t0\n> +#define QCOM_HYP_BOOT_TYPE_KVM\t\t\t1\n> +\n> +/* TCR_EL2 bit field definitions */\n> +#define TCR_T0SZ_MASK\t\t\t\t0x1FUL\n> +#define TCR_PS_MASK\t\t\t\t(0x7UL << 32)\n> +#define TCR_PS_SHIFT\t\t\t\t16\n> +#define TCR_SH_ORGN_IRGN_MASK\t\t\t0x3F00UL\n> +#define TCR_SH_INNER_SHAREABLE\t\t\t(3UL << 12)\n> +#define TCR_ORGN_WRITE_BACK_ALLOC\t\tBIT(10)\n> +#define TCR_IRGN_WRITE_BACK_ALLOC\t\tBIT(8)\n> +\n> #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)\n> void qcom_configure_capsule_updates(void);\n> #else","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=NNoF7cTx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=linaro.org","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org 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at 11:08:29PM +0530, Aswin Murugan wrote:\n> Enable Linux KVM virtualization on Snapdragon SoCs.\n> \n> Introduce CONFIG_QCOM_KVM_SUPPORT to select KVM or Gunyah\n> hypervisor modes at build time.\n> \n> qcom-priv.h:\n> - Add TrustZone SMC interface definitions and parameter IDs\n> - Define hypervisor boot types (GUNYAH=0, KVM=1)\n> - Add TCR_EL2 bit field definitions for memory config\n> \n> board.c:\n> - Add qcom_configure_kvm_hypervisor() with EL-aware logic\n> - EL2: Perform direct SMC call for hypervisor setup\n> - EL1: Save context, disable caches, run SMC, restore state,\n> reconfigure TCR_EL2, re-enable caches\n\nPlease don't switch EL1 -> EL2 in the middle of U-Boot execution which\njust adds these expensive MMU operations during boot.\n\nRather than that just follow the upstream edk2 example to switch from\nEL1 -> EL2 on the first platform specific init code code sequence. Have\na look at this reference [1]. Surely you can keep the switch under a\nconfig option. This will make U-Boot to properly execute either in EL1\nor EL2.\n\n[1] https://github.com/tianocore/edk2-platforms/blob/master/Silicon/Qualcomm/KodiakPkg/Library/KodiakLib/KodiakHelper.S\n\n-Sumit\n\n> - Add qcom_configure_gunyah_hypervisor() for standard flow\n> - Add SCM service availability checks\n> \n> Default mode remains Gunyah. Enable CONFIG_QCOM_KVM_SUPPORT to\n> select KVM for Linux.\n> \n> Signed-off-by: Aswin Murugan \n> ---\n> arch/arm/mach-snapdragon/Kconfig | 7 ++\n> arch/arm/mach-snapdragon/board.c | 154 +++++++++++++++++++++++++++\n> arch/arm/mach-snapdragon/qcom-priv.h | 31 ++++++\n> 3 files changed, 192 insertions(+)\n> \n> diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig\n> index d3de8693b5a..2e5676945ca 100644\n> --- a/arch/arm/mach-snapdragon/Kconfig\n> +++ b/arch/arm/mach-snapdragon/Kconfig\n> @@ -42,4 +42,11 @@ config SYS_CONFIG_NAME\n> \t Based on this option include/configs/.h header\n> \t will be used for board configuration.\n> \n> +config QCOM_KVM_SUPPORT\n> +\tbool \"Enable KVM support for Qualcomm platforms\"\n> +\tdepends on ARM64\n> +\thelp\n> +\t This configures the hypervisor interface during boot to support\n> +\t KVM virtualization instead of the default Gunyah hypervisor.\n> +\n> endif\n> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\n> index 5fb3240acc5..2926dd8ccc0 100644\n> --- a/arch/arm/mach-snapdragon/board.c\n> +++ b/arch/arm/mach-snapdragon/board.c\n> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)\n> {\n> }\n> \n> +/**\n> + * qcom_configure_kvm_hypervisor() - Configure hypervisor for KVM guest mode\n> + *\n> + * Configures the hypervisor for KVM operation:\n> + * - EL2 path: Direct SMC call\n> + * - EL1 path: Save context, disable caches, SMC call, restore context\n> + *\n> + * Return: 0 on success, negative error code on failure\n> + */\n> +static int qcom_configure_kvm_hypervisor(void)\n> +{\n> +\tstruct arm_smccc_res res;\n> +\tu64 current_el;\n> +\n> +\tasm volatile(\"mrs %0, CurrentEL\" : \"=r\" (current_el));\n> +\tcurrent_el = (current_el >> 2) & 0x3;\n> +\n> +\tlog_info(\"Configuring hypervisor for KVM (EL%llu)\\n\", current_el);\n> +\n> +\tarm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,\n> +\t\t TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t 0, 0, 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0)\n> +\t\tlog_debug(\"KVM milestone service not available (0x%lx)\\n\", res.a0);\n> +\n> +\tif (current_el == 2) {\n> +\t\tlog_debug(\"At EL2\\n\");\n> +\n> +\t\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n> +\t\t\t 0, 0, QCOM_HYP_BOOT_TYPE_KVM,\n> +\t\t\t 0, 0, 0, &res);\n> +\n> +\t\tif (res.a0 != 0) {\n> +\t\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n> +\t\t\treturn -EIO;\n> +\t\t}\n> +\n> +\t\tlog_info(\"KVM hypervisor configured\\n\");\n> +\t\treturn 0;\n> +\t}\n> +\n> +\tlog_debug(\"At EL1, saving register context\\n\");\n> +\n> +\tu64 ttbr0_el1, tcr_el1, tcr_el2, mair_el1;\n> +\tu64 t0sz, phys_addr_size;\n> +\n> +\t/* Save EL1 system register context */\n> +\tasm volatile(\"mrs %0, ttbr0_el1\" : \"=r\" (ttbr0_el1));\n> +\tasm volatile(\"mrs %0, tcr_el1\" : \"=r\" (tcr_el1));\n> +\tasm volatile(\"mrs %0, mair_el1\" : \"=r\" (mair_el1));\n> +\n> +\tt0sz = tcr_el1 & TCR_T0SZ_MASK;\n> +\tphys_addr_size = tcr_el1 & TCR_PS_MASK;\n> +\n> +\tlog_debug(\"Saved context: TTBR0=0x%llx TCR=0x%llx MAIR=0x%llx\\n\",\n> +\t\t ttbr0_el1, tcr_el1, mair_el1);\n> +\n> +\ticache_disable();\n> +\tdcache_disable();\n> +\n> +\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n> +\t\t 0, 0, QCOM_HYP_BOOT_TYPE_KVM,\n> +\t\t 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0) {\n> +\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n> +\t\ticache_enable();\n> +\t\tdcache_enable();\n> +\t\treturn -EIO;\n> +\t}\n> +\n> +\tasm volatile(\"mrs %0, CurrentEL\" : \"=r\" (current_el));\n> +\tcurrent_el = (current_el >> 2) & 0x3;\n> +\n> +\tasm volatile(\"msr ttbr0_el1, %0\" : : \"r\" (ttbr0_el1));\n> +\tasm volatile(\"isb\");\n> +\n> +\tif (current_el != 2) {\n> +\t\tlog_debug(\"No EL2 transition, skipping TCR_EL2 config\\n\");\n> +\t\ticache_enable();\n> +\t\tdcache_enable();\n> +\t\tlog_warning(\"KVM hypervisor configuration failed\\n\");\n> +\t\treturn 0;\n> +\t}\n> +\n> +\t/* Read current TCR_EL2 and reconfigure it */\n> +\tasm volatile(\"mrs %0, tcr_el2\" : \"=r\" (tcr_el2));\n> +\n> +\ttcr_el2 &= ~(TCR_T0SZ_MASK | (0x7UL << 16));\n> +\ttcr_el2 |= t0sz | (phys_addr_size >> TCR_PS_SHIFT);\n> +\n> +\ttcr_el2 &= ~TCR_SH_ORGN_IRGN_MASK;\n> +\ttcr_el2 |= TCR_SH_INNER_SHAREABLE |\n> +\t\t TCR_ORGN_WRITE_BACK_ALLOC |\n> +\t\t TCR_IRGN_WRITE_BACK_ALLOC;\n> +\n> +\tasm volatile(\"msr tcr_el2, %0\" : : \"r\" (tcr_el2));\n> +\tasm volatile(\"msr mair_el1, %0\" : : \"r\" (mair_el1));\n> +\tasm volatile(\"isb\");\n> +\n> +\ticache_enable();\n> +\tdcache_enable();\n> +\n> +\tlog_info(\"KVM hypervisor configured\\n\");\n> +\treturn 0;\n> +}\n> +\n> +/**\n> + * qcom_configure_gunyah_hypervisor() - Configure hypervisor for Gunyah mode\n> + *\n> + * Configures the hypervisor for standard Gunyah operation.\n> + *\n> + * Return: 0 on success, negative error code on failure\n> + */\n> +static int qcom_configure_gunyah_hypervisor(void)\n> +{\n> +\tstruct arm_smccc_res res;\n> +\n> +\tlog_info(\"Configuring hypervisor for Gunyah mode\\n\");\n> +\n> +\tarm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,\n> +\t\t TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t 0, 0, 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0) {\n> +\t\tlog_debug(\"Hypervisor milestone service not available (0x%lx)\\n\", res.a0);\n> +\t\treturn 0;\n> +\t}\n> +\n> +\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n> +\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n> +\t\t 0, 0, QCOM_HYP_BOOT_TYPE_GUNYAH,\n> +\t\t 0, 0, 0, &res);\n> +\n> +\tif (res.a0 != 0) {\n> +\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n> +\t\treturn -EIO;\n> +\t}\n> +\n> +\tlog_info(\"Gunyah hypervisor configured\\n\");\n> +\treturn 0;\n> +}\n> +\n> #define KERNEL_COMP_SIZE\tSZ_64M\n> arch/arm/mach-snapdragon/Kconfig #ifdef CONFIG_FASTBOOT_BUF_SIZE\n> #define FASTBOOT_BUF_SIZE CONFIG_FASTBOOT_BUF_SIZE\n> @@ -570,6 +718,12 @@ int board_late_init(void)\n> \tqcom_late_init();\n> \n> \tqcom_show_boot_source();\n> +\n> +\tif (IS_ENABLED(CONFIG_QCOM_KVM_SUPPORT))\n> +\t\tqcom_configure_kvm_hypervisor();\n> +\telse\n> +\t\tqcom_configure_gunyah_hypervisor();\n> +\n> \t/* Configure the dfu_string for capsule updates */\n> \tqcom_configure_capsule_updates();\n> \n> diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h\n> index b8bf574e8bb..a5d9dec6aa7 100644\n> --- a/arch/arm/mach-snapdragon/qcom-priv.h\n> +++ b/arch/arm/mach-snapdragon/qcom-priv.h\n> @@ -17,6 +17,37 @@ enum qcom_boot_source {\n> \n> extern enum qcom_boot_source qcom_boot_source;\n> \n> +/* TrustZone SMC definitions */\n> +#define TZ_SYSCALL_CREATE_SMC_ID(o, s, f) \\\n> +\t((u32)((((o) & 0x3f) << 24) | (((s) & 0xff) << 8) | ((f) & 0xff)))\n> +\n> +#define TZ_OWNER_SIP\t\t\t\t2\n> +#define TZ_SVC_BOOT\t\t\t\t1\n> +#define TZ_SVC_INFO\t\t\t\t6\n> +#define TZ_BOOT_CMD_KVM_MILESTONE\t\t0x21\n> +#define TZ_INFO_IS_SVC_AVAILABLE_CMD\t\t0x01\n> +\n> +#define TZ_CONFIGURE_MILESTONE_SERVICE_ID \\\n> +\tTZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_SIP, TZ_SVC_BOOT, TZ_BOOT_CMD_KVM_MILESTONE)\n> +#define TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID\t\t0x23\n> +\n> +#define TZ_INFO_IS_SVC_AVAILABLE_ID \\\n> +\tTZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_SIP, TZ_SVC_INFO, TZ_INFO_IS_SVC_AVAILABLE_CMD)\n> +#define TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID\t\t0x1\n> +\n> +/* Hypervisor boot types */\n> +#define QCOM_HYP_BOOT_TYPE_GUNYAH\t\t0\n> +#define QCOM_HYP_BOOT_TYPE_KVM\t\t\t1\n> +\n> +/* TCR_EL2 bit field definitions */\n> +#define TCR_T0SZ_MASK\t\t\t\t0x1FUL\n> +#define TCR_PS_MASK\t\t\t\t(0x7UL << 32)\n> +#define TCR_PS_SHIFT\t\t\t\t16\n> +#define TCR_SH_ORGN_IRGN_MASK\t\t\t0x3F00UL\n> +#define TCR_SH_INNER_SHAREABLE\t\t\t(3UL << 12)\n> +#define TCR_ORGN_WRITE_BACK_ALLOC\t\tBIT(10)\n> +#define TCR_IRGN_WRITE_BACK_ALLOC\t\tBIT(8)\n> +\n> #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)\n> void qcom_configure_capsule_updates(void);\n> #else\n> -- \n> 2.34.1\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=umDXoarn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=kernel.org","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org 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JOIFvkNx6phBNEavv1+3dBc9Ihr5t2HdDal9YLIiQqXnur2DKxlhnYTck39YBvZEQC\n 6Vq8PPD5mMMDabp3Cuv/dUHy1x+IHL1fsOYtrlMeO8b0ZER4c0Szq1g3PgJGv4Pe70\n y2FOdXQWleTsuhub/l9XsHeeegspOzKzoz+eNNaFFcs4mGjtqjbWa3pSFakcGi5rce\n T+R0aCpIp7+92z/dYjLNluYNJf0qAC2V5X7y66pkWyh721icFC+dRC2ci9yMtlQp0b\n 2K/Sg+NE1JdbA==","Date":"Mon, 20 Apr 2026 19:15:13 +0530","From":"Sumit Garg ","To":"Aswin Murugan ","Cc":"trini@konsulko.com, casey.connolly@linaro.org,\n neil.armstrong@linaro.org, sughosh.ganu@arm.com,\n gchan9527@gmail.com, u-boot-qcom@groups.io, u-boot@lists.denx.de","Subject":"Re: [PATCH v1] mach-snapdragon: Add KVM hypervisor support","Message-ID":"","References":"<20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com>","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3680594,"web_url":"http://patchwork.ozlabs.org/comment/3680594/","msgid":"","list_archive_url":null,"date":"2026-04-22T09:13:44","subject":"Re: [PATCH v1] mach-snapdragon: Add KVM hypervisor support","submitter":{"id":90838,"url":"http://patchwork.ozlabs.org/api/people/90838/","name":"Pavan Kondeti","email":"pavan.kondeti@oss.qualcomm.com"},"content":"On Mon, Apr 20, 2026 at 07:15:13PM +0530, Sumit Garg wrote:\n> On Sun, Apr 19, 2026 at 11:08:29PM +0530, Aswin Murugan wrote:\n> > Enable Linux KVM virtualization on Snapdragon SoCs.\n> > \n> > Introduce CONFIG_QCOM_KVM_SUPPORT to select KVM or Gunyah\n> > hypervisor modes at build time.\n> > \n> > qcom-priv.h:\n> > - Add TrustZone SMC interface definitions and parameter IDs\n> > - Define hypervisor boot types (GUNYAH=0, KVM=1)\n> > - Add TCR_EL2 bit field definitions for memory config\n> > \n> > board.c:\n> > - Add qcom_configure_kvm_hypervisor() with EL-aware logic\n> > - EL2: Perform direct SMC call for hypervisor setup\n> > - EL1: Save context, disable caches, run SMC, restore state,\n> > reconfigure TCR_EL2, re-enable caches\n> \n> Please don't switch EL1 -> EL2 in the middle of U-Boot execution which\n> just adds these expensive MMU operations during boot.\n> \n> Rather than that just follow the upstream edk2 example to switch from\n> EL1 -> EL2 on the first platform specific init code code sequence. Have\n> a look at this reference [1]. Surely you can keep the switch under a\n> config option. This will make U-Boot to properly execute either in EL1\n> or EL2.\n> \n> [1] https://github.com/tianocore/edk2-platforms/blob/master/Silicon/Qualcomm/KodiakPkg/Library/KodiakLib/KodiakHelper.S\n> \n\nThanks Sumit for pointing this out. In one of our implementation, we are doing \nthis EL1->EL2 switch as part of ExitBootServices(). As you mentioned in the commit\ndescription [1] , this seems one step closer to recommended boot flow.\n\nThanks,\nPavan\n\n[1]\nhttps://github.com/tianocore/edk2-platforms/commit/0a51cc11dd74be199c67eceabc7bf68d36bb7075","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=dspuCLDI;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=cPLmbBDj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"dspuCLDI\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"cPLmbBDj\";\n\tdkim-atps=neutral","phobos.denx.de; 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