[{"id":3679832,"web_url":"http://patchwork.ozlabs.org/comment/3679832/","msgid":"","list_archive_url":null,"date":"2026-04-21T11:40:55","subject":"Re: [PATCH v2] pwm: atmel-tcb: Cache clock rates and mark chip as\n atomic","submitter":{"id":88416,"url":"http://patchwork.ozlabs.org/api/people/88416/","name":"Uwe Kleine-König","email":"ukleinek@kernel.org"},"content":"Hello Sangyun,\n\nOn Sun, Apr 19, 2026 at 05:08:38PM +0900, Sangyun Kim wrote:\n> @@ -438,16 +441,33 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)\n> \tif (err)\n> \t\tgoto err_gclk;\n> \n> +\terr = clk_rate_exclusive_get(tcbpwmc->clk);\n> +\tif (err)\n> +\t\tgoto err_disable_clk;\n> +\n> +\terr = clk_rate_exclusive_get(tcbpwmc->slow_clk);\n> +\tif (err)\n> +\t\tgoto err_clk_unlock;\n> +\n> +\ttcbpwmc->rate = clk_get_rate(tcbpwmc->clk);\n> +\ttcbpwmc->slow_rate = clk_get_rate(tcbpwmc->slow_clk);\n> +\n\nOnly one concern left: clk_get_rate() should only be called on enabled\nclocks. I don't know the architecture details and how expensive it is to\nhave .clk enabled (or if it's enabled anyhow).\n\nIf you're ok, I'd squash the following diff into your patch:\n\ndiff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c\nindex 1a2832f1ace2..3d30aeab507e 100644\n--- a/drivers/pwm/pwm-atmel-tcb.c\n+++ b/drivers/pwm/pwm-atmel-tcb.c\n@@ -437,13 +437,17 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)\n \ttcbpwmc->channel = channel;\n \ttcbpwmc->width = config->counter_width;\n \n-\terr = clk_prepare_enable(tcbpwmc->slow_clk);\n+\terr = clk_prepare_enable(tcbpwmc->clk);\n \tif (err)\n \t\tgoto err_gclk;\n \n+\terr = clk_prepare_enable(tcbpwmc->slow_clk);\n+\tif (err)\n+\t\tgoto err_disable_clk;;\n+\n \terr = clk_rate_exclusive_get(tcbpwmc->clk);\n \tif (err)\n-\t\tgoto err_disable_clk;\n+\t\tgoto err_disable_slow_clk;\n \n \terr = clk_rate_exclusive_get(tcbpwmc->slow_clk);\n \tif (err)\n@@ -469,6 +473,9 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)\n \tclk_rate_exclusive_put(tcbpwmc->clk);\n \n err_disable_clk:\n+\tclk_disable_unprepare(tcbpwmc->clk);\n+\n+err_disable_slow_clk:\n \tclk_disable_unprepare(tcbpwmc->slow_clk);\n \n err_gclk:\n@@ -492,6 +499,7 @@ static void atmel_tcb_pwm_remove(struct platform_device *pdev)\n \n \tclk_rate_exclusive_put(tcbpwmc->slow_clk);\n \tclk_rate_exclusive_put(tcbpwmc->clk);\n+\tclk_disable_unprepare(tcbpwmc->clk);\n \tclk_disable_unprepare(tcbpwmc->slow_clk);\n \tclk_put(tcbpwmc->gclk);\n \tclk_put(tcbpwmc->clk);\n\n\nThis has the downside that clk is kept enabled the whole driver\nlifetime, but that's the easiest way to make your fix honor the clk API\nconstraints. This allows to fast-track the patch fixing the sleeping\nfunction called from invalid context issue and the optimisation can then\nbe addressed with more time during the next development cycles.\n\nBest regards\nUwe","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=JnHmsRiS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8664-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"JnHmsRiS\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0L5p6CwJz1yGt\n\tfor ; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"zmlydvd5ruato4sk\"","Content-Disposition":"inline","In-Reply-To":"<20260419080838.3192357-1-sangyun.kim@snu.ac.kr>"}},{"id":3680221,"web_url":"http://patchwork.ozlabs.org/comment/3680221/","msgid":"<20260422044940.tse3ek7jlv3x2dbt@nunu>","list_archive_url":null,"date":"2026-04-22T04:49:40","subject":"Re: [PATCH v2] pwm: atmel-tcb: Cache clock rates and mark chip as\n atomic","submitter":{"id":93159,"url":"http://patchwork.ozlabs.org/api/people/93159/","name":"Sangyun Kim","email":"sangyun.kim@snu.ac.kr"},"content":"On Tue, Apr 21, 2026 at 01:40:55 PM +0200, Uwe Kleine-König wrote:\n>Hello Sangyun,\n\nHi Uwe,\nThanks for the review.\n\n>\n>On Sun, Apr 19, 2026 at 05:08:38PM +0900, Sangyun Kim wrote:\n>> @@ -438,16 +441,33 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)\n>> \tif (err)\n>> \t\tgoto err_gclk;\n>>\n>> +\terr = clk_rate_exclusive_get(tcbpwmc->clk);\n>> +\tif (err)\n>> +\t\tgoto err_disable_clk;\n>> +\n>> +\terr = clk_rate_exclusive_get(tcbpwmc->slow_clk);\n>> +\tif (err)\n>> +\t\tgoto err_clk_unlock;\n>> +\n>> +\ttcbpwmc->rate = clk_get_rate(tcbpwmc->clk);\n>> +\ttcbpwmc->slow_rate = clk_get_rate(tcbpwmc->slow_clk);\n>> +\n>\n>Only one concern left: clk_get_rate() should only be called on enabled\n>clocks. I don't know the architecture details and how expensive it is to\n>have .clk enabled (or if it's enabled anyhow).\n>\n>If you're ok, I'd squash the following diff into your patch:\n\nThat makes sense. clk_get_rate() should indeed only be used on enabled\nclocks, and your change is the simplest way to ensure correctness while\nrespecting the clk API constraints. I’m happy with squashing your diff\ninto my patch.\n\n>\n>diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c\n>index 1a2832f1ace2..3d30aeab507e 100644\n>--- a/drivers/pwm/pwm-atmel-tcb.c\n>+++ b/drivers/pwm/pwm-atmel-tcb.c\n>@@ -437,13 +437,17 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)\n> \ttcbpwmc->channel = channel;\n> \ttcbpwmc->width = config->counter_width;\n>\n>-\terr = clk_prepare_enable(tcbpwmc->slow_clk);\n>+\terr = clk_prepare_enable(tcbpwmc->clk);\n> \tif (err)\n> \t\tgoto err_gclk;\n>\n>+\terr = clk_prepare_enable(tcbpwmc->slow_clk);\n>+\tif (err)\n>+\t\tgoto err_disable_clk;;\n>+\n> \terr = clk_rate_exclusive_get(tcbpwmc->clk);\n> \tif (err)\n>-\t\tgoto err_disable_clk;\n>+\t\tgoto err_disable_slow_clk;\n>\n> \terr = clk_rate_exclusive_get(tcbpwmc->slow_clk);\n> \tif (err)\n>@@ -469,6 +473,9 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)\n> \tclk_rate_exclusive_put(tcbpwmc->clk);\n>\n> err_disable_clk:\n>+\tclk_disable_unprepare(tcbpwmc->clk);\n>+\n>+err_disable_slow_clk:\n> \tclk_disable_unprepare(tcbpwmc->slow_clk);\n>\n> err_gclk:\n>@@ -492,6 +499,7 @@ static void atmel_tcb_pwm_remove(struct platform_device *pdev)\n>\n> \tclk_rate_exclusive_put(tcbpwmc->slow_clk);\n> \tclk_rate_exclusive_put(tcbpwmc->clk);\n>+\tclk_disable_unprepare(tcbpwmc->clk);\n> \tclk_disable_unprepare(tcbpwmc->slow_clk);\n> \tclk_put(tcbpwmc->gclk);\n> \tclk_put(tcbpwmc->clk);\n>\n>\n>This has the downside that clk is kept enabled the whole driver\n>lifetime, but that's the easiest way to make your fix honor the clk API\n>constraints. This allows to fast-track the patch fixing the sleeping\n>function called from invalid context issue and the optimisation can then\n>be addressed with more time during the next development cycles.\n\nKeeping the clock enabled for the driver lifetime is acceptable for now\nto fast-track the fix, and we can revisit potential optimizations in a\nfollow-up patch.\n\nThanks again for the suggestion.\n\n>\n>Best regards\n>Uwe\n\nBest regards,\nSangyun","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=snu.ac.kr header.i=@snu.ac.kr header.a=rsa-sha256\n header.s=google header.b=G8K0zuPy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8668-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=snu.ac.kr header.i=@snu.ac.kr\n header.b=\"G8K0zuPy\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.214.179","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=snu.ac.kr","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=snu.ac.kr"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0n1M5G4Yz1y2d\n\tfor ; Wed, 22 Apr 2026 14:53:43 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 4093E3055821\n\tfor ; Wed, 22 Apr 2026 04:49:48 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id ED3672652A2;\n\tWed, 22 Apr 2026 04:49:47 +0000 (UTC)","from mail-pl1-f179.google.com (mail-pl1-f179.google.com\n [209.85.214.179])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D5A0277007\n\tfor ; Wed, 22 Apr 2026 04:49:44 +0000 (UTC)","by mail-pl1-f179.google.com with SMTP id\n d9443c01a7336-2b23fcf90b2so48265585ad.3\n for ; Tue, 21 Apr 2026 21:49:44 -0700 (PDT)","from localhost (nunu.snu.ac.kr. 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charset=utf-8; format=flowed","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":""}},{"id":3681967,"web_url":"http://patchwork.ozlabs.org/comment/3681967/","msgid":"","list_archive_url":null,"date":"2026-04-24T10:46:00","subject":"Re: [PATCH v2] pwm: atmel-tcb: Cache clock rates and mark chip as\n atomic","submitter":{"id":88416,"url":"http://patchwork.ozlabs.org/api/people/88416/","name":"Uwe Kleine-König","email":"ukleinek@kernel.org"},"content":"Hello Sangyun,\n\nOn Wed, Apr 22, 2026 at 01:49:40PM +0900, Sangyun Kim wrote:\n> > On Sun, Apr 19, 2026 at 05:08:38PM +0900, Sangyun Kim wrote:\n> > > @@ -438,16 +441,33 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)\n> > > \tif (err)\n> > > \t\tgoto err_gclk;\n> > > \n> > > +\terr = clk_rate_exclusive_get(tcbpwmc->clk);\n> > > +\tif (err)\n> > > +\t\tgoto err_disable_clk;\n> > > +\n> > > +\terr = clk_rate_exclusive_get(tcbpwmc->slow_clk);\n> > > +\tif (err)\n> > > +\t\tgoto err_clk_unlock;\n> > > +\n> > > +\ttcbpwmc->rate = clk_get_rate(tcbpwmc->clk);\n> > > +\ttcbpwmc->slow_rate = clk_get_rate(tcbpwmc->slow_clk);\n> > > +\n> > \n> > Only one concern left: clk_get_rate() should only be called on enabled\n> > clocks. I don't know the architecture details and how expensive it is to\n> > have .clk enabled (or if it's enabled anyhow).\n> > \n> > If you're ok, I'd squash the following diff into your patch:\n> \n> That makes sense. clk_get_rate() should indeed only be used on enabled\n> clocks, and your change is the simplest way to ensure correctness while\n> respecting the clk API constraints. I’m happy with squashing your diff\n> into my patch.\n\nJust for the record: I did that, the result is already in Linus' tree\nat https://git.kernel.org/linus/68637b68afcc3cb4d56aca14a3a1d1b47b879369\nand will be part of v7.1-rc1.\n\nBest regards\nUwe","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=pFpfhwgD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8689-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"pFpfhwgD\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g28l32vsXz1yDD\n\tfor ; Fri, 24 Apr 2026 20:46:07 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id E297D300145B\n\tfor ; Fri, 24 Apr 2026 10:46:04 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E31772882BE;\n\tFri, 24 Apr 2026 10:46:02 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id B75672D3EF2;\n\tFri, 24 Apr 2026 10:46:02 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 24BF6C19425;\n\tFri, 24 Apr 2026 10:46:01 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777027562; cv=none;\n b=YuFeFxY4VY1KcvdRA6b87h6FKycLo76jhPNLFORWuhpPj66eCkSE4XLLQLnEAVitUZOaJR/cGx55zQHeyGSZeRL31DMwG7FQca8FL+jN3gP3+qyxBYA7zAeoIZN0xMPnrSE0KuBQTpWd3BepU6xQ0LCebp4ljlK/pvWLgJ5aOKQ=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777027562; c=relaxed/simple;\n\tbh=wdjDn556jbNQ7WzXeovxIVH/s2CXei4diJaRwgeH7JQ=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=DVQbuar2yOmrJ2CwI/MwvFaNDtmD1nY9t/8rHWBtm+nE0uGynhsnNOior20KbvEOa6IWIMtLc2QbP2x4pf0kvGUXJlHuYd/xV323RxjxL6DgtGDj+Xscz5qI9ysJ2JDg6me+yRu3tBaVF75qgfx0egAcm+XiVAPwPi+SE3l1dTI=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=pFpfhwgD; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777027562;\n\tbh=wdjDn556jbNQ7WzXeovxIVH/s2CXei4diJaRwgeH7JQ=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=pFpfhwgDLwVhkonHJohzjlaMdgRTAV05QdGH90A4J3liKHg1pMfsHoIlIA8JYM4/u\n\t KM5X9kK4PESEn1AMXMrr8e9TfO+Eqf2c63LsY/dR73mWFVuxOHH4iKTmcQDoAKhwsX\n\t tvmDyC5AHyIJKb5kXi+LQLP4+Il4P/bOZBTeEQ1jDstDfgUavlZsFqlc7p0f6qSzBj\n\t HkUUNMXXU/bQdRDaPPuPsIYhFRWA7ILKrMG5DaKJxtCV9JXU0WCUudSaQDq1w4zdPc\n\t otMC2pBvlhRjkLcOf/hmdVvfOC/9xE/n7OORCFHJGdo790iqZFZdByPUlCp7dqDlvP\n\t 2EaQbZO3rfysA==","Date":"Fri, 24 Apr 2026 12:46:00 +0200","From":"Uwe =?utf-8?q?Kleine-K=C3=B6nig?= ","To":"Sangyun Kim ","Cc":"nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com,\n\tclaudiu.beznea@tuxon.dev, linux-pwm@vger.kernel.org,\n linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org","Subject":"Re: [PATCH v2] pwm: atmel-tcb: Cache clock rates and mark chip as\n atomic","Message-ID":"","References":"<20260415093433.2359955-1-sangyun.kim@snu.ac.kr>\n <20260419080838.3192357-1-sangyun.kim@snu.ac.kr>\n \n <20260422044940.tse3ek7jlv3x2dbt@nunu>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"xeni4cw4nw33ej5e\"","Content-Disposition":"inline","In-Reply-To":"<20260422044940.tse3ek7jlv3x2dbt@nunu>"}}]