[{"id":3678985,"web_url":"http://patchwork.ozlabs.org/comment/3678985/","msgid":"","list_archive_url":null,"date":"2026-04-18T17:05:05","subject":"Re: [PATCH] bitintlower: Padding bit fixes, part 3 [PR123635]","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/people/92310/","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"content":"On 4/18/2026 9:21 AM, Jakub Jelinek wrote:\n> Hi!\n>\n> I've debugged the rest of the failures on riscv64-linux (in particular\n> torture/bitint-{87,89}.c FAILs at -O2).\n> This is on top of https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713242.html\n> patch.\n> One problem was that the lower_shift_stmt RSHIFT_EXPR change to iterate\n> until p2 rather than p (where p2 is p + 1 if bitint_ext_full and there is\n> full limb of padding bits), the loop is emitted with a condition before the\n> header and another condition before the latch edge and I've mistakenly fixed\n> just the latter and not the former.\n> ANother problem was that in all the 3 RSHIFT_EXPRs added meant to set\n> a full limb to 0 or all ones based on most significant bit I've mistakenly used\n> unsigned type rather than signed, so it was set to 0 or 1 instead (this\n> was twice in lower_shift_stmt, for the LSHIFT_EXPR case in both cases and\n> once in lower_float_conv_stmt).\n> And finally, because unsigned MULT_EXPR doesn't have overflow undefined, we\n> actually don't need to just clear the full padding bit limb (if any) but\n> even the padding bits in the partial limb (if any; and this actually doesn't\n> affect just arm and riscv, but also affects s390x and loongarch).\n>\n> Tested with\n> make -j8 -k check-gcc GCC_TEST_RUN_EXPENSIVE=1 RUNTESTFLAGS=\"GCC_TEST_RUN_EXPENSIVE=1 dg.exp='*bitint* pr112673.c builtin-stdc-bit-*.c pr112566-2.c pr112511.c pr116588.c pr116003.c pr113693.c pr113602.c flex-array-counted-by-7.c' dg-torture.exp='*bitint* pr116480-2.c pr114312.c pr114121.c' dfp.exp=*bitint* vect.exp='vect-early-break_99-pr113287.c' tree-ssa.exp=pr113735.c\"\n> on riscv64-linux, ok for trunk if it passes full bootstrap/regtest on\n> x86_64-linux, i686-linux, aarch64-linux and s390x-linux too?\n>\n> 2026-04-18 Jakub Jelinek \n>\n> \tPR middle-end/123635\n> \t* gimple-lower-bitint.cc (bitint_large_huge::lower_shift_stmt): In the\n> \tRSHIFT_EXPR case, use p2 in two LE_EXPR conditions rather than just\n> \tone. In LSHIFT_EXPR case, use signed RSHIFT_EXPR instead of unsigned.\n> \t(bitint_large_huge::lower_muldiv_stmt): For unsigned MULT_EXPR with\n> \tbitint_extended if prec is not multiple of limb_prec, clear padding\n> \tbits after libgcc call.\n> \t(bitint_large_huge::lower_float_conv_stmt): Use signed RSHIFT_EXPR\n> \tinstead of unsigned.\nSimilary, I'll throw this into the tester, but this time testing both \npatches across the full set of targets.  Your call on the implementation \nbits in gimple-lower-bitinit IMHO.\n\njeff","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=g9n80x0u;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=MPbWzwd4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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and this actually doesn't\n> affect just arm and riscv, but also affects s390x and loongarch).\n>\n> Tested with\n> make -j8 -k check-gcc GCC_TEST_RUN_EXPENSIVE=1 RUNTESTFLAGS=\"GCC_TEST_RUN_EXPENSIVE=1 dg.exp='*bitint* pr112673.c builtin-stdc-bit-*.c pr112566-2.c pr112511.c pr116588.c pr116003.c pr113693.c pr113602.c flex-array-counted-by-7.c' dg-torture.exp='*bitint* pr116480-2.c pr114312.c pr114121.c' dfp.exp=*bitint* vect.exp='vect-early-break_99-pr113287.c' tree-ssa.exp=pr113735.c\"\n> on riscv64-linux, ok for trunk if it passes full bootstrap/regtest on\n> x86_64-linux, i686-linux, aarch64-linux and s390x-linux too?\n>\n> 2026-04-18 Jakub Jelinek \n>\n> \tPR middle-end/123635\n> \t* gimple-lower-bitint.cc (bitint_large_huge::lower_shift_stmt): In the\n> \tRSHIFT_EXPR case, use p2 in two LE_EXPR conditions rather than just\n> \tone. In LSHIFT_EXPR case, use signed RSHIFT_EXPR instead of unsigned.\n> \t(bitint_large_huge::lower_muldiv_stmt): For unsigned MULT_EXPR with\n> \tbitint_extended if prec is not multiple of limb_prec, clear padding\n> \tbits after libgcc call.\n> \t(bitint_large_huge::lower_float_conv_stmt): Use signed RSHIFT_EXPR\n> \tinstead of unsigned.\nAnd this fixed -87 and -89.  No regressions across the embedded targets \nor x86 native.\n\njeff","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=J8codnlM;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=GZ3BDAEl;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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