[{"id":3679207,"web_url":"http://patchwork.ozlabs.org/comment/3679207/","msgid":"","list_archive_url":null,"date":"2026-04-20T04:06:40","subject":"Re: [PATCH v3 2/7] mach-snapdragon: Add FIT multi-DTB selection\n support","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"Hi Aswin,\n\nOn 2026-04-17T12:09:44, Aswin Murugan wrote:\n> mach-snapdragon: Add FIT multi-DTB selection support\n>\n> Implement multi DTB selection from FIT images based on hardware\n> detection via SMEM.\n>\n> The implementation provides:\n>\n> 1. Hardware Detection: Reads SoC parameters from SMEM including chip ID,\n> version, platform ID, OEM variant, DDR size, and storage type from IMEM.\n>\n> 2. Metadata DTB Processing: Parses a metadata DTB (first image in FIT)\n> to build a \"bucket list\" of hardware-specific node names that match\n> the detected hardware parameters.\n>\n> 3. FIT Configuration Matching: Uses standard FIT mechanisms to find the\n> configuration with the most matching tokens in its compatible string\n> compared to the hardware-derived bucket list.\n>\n> 4. DTB Loading and Overlays: Loads the base DTB and applies any DTBOs\n> specified in the selected configuration using standard FIT overlay\n> [...]\n>\n> arch/arm/mach-snapdragon/Kconfig | 8 +\n> arch/arm/mach-snapdragon/Makefile | 1 +\n> arch/arm/mach-snapdragon/board.c | 7 +\n> arch/arm/mach-snapdragon/qcom_fit_multidtb.c | 1103 ++++++++++++++++++++++++++\n> arch/arm/mach-snapdragon/qcom_fit_multidtb.h | 189 +++++\n> 5 files changed, 1308 insertions(+)\n\n> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\n> @@ -585,6 +586,12 @@ int board_late_init(void)\n> + /* Try FIT multi-DTB selection if enabled */\n> + if (IS_ENABLED(CONFIG_QCOM_FIT_MULTIDTB)) {\n> + if (!qcom_fit_multidtb_setup())\n> + log_debug(\"FIT multi-DTB selection not available or failed\\n\");\n> + }\n\nThe logic seems inverted, since qcom_fit_multidtb_setup() returns 0 on success.\n\n> diff --git a/arch/arm/mach-snapdragon/qcom_fit_multidtb.c b/arch/arm/mach-snapdragon/qcom_fit_multidtb.c\n> @@ -0,0 +1,1103 @@\n> +#define TCSR_SOC_HW_VERSION 0x01fc8000\n\nThis address is hardcoded - does this mean the same TCSR base is used\non all SoCs?\n\n> diff --git a/arch/arm/mach-snapdragon/qcom_fit_multidtb.c b/arch/arm/mach-snapdragon/qcom_fit_multidtb.c\n> @@ -0,0 +1,1103 @@\n> + *ddr_type = 0;\n> + if (total_ddr_size <= DDR_128MB)\n> + *ddr_type = DDRTYPE_128MB;\n> + else if (total_ddr_size <= DDR_256MB)\n> + *ddr_type = DDRTYPE_256MB;\n> + else if (total_ddr_size <= DDR_512MB)\n> + *ddr_type = DDRTYPE_512MB;\n> + else if (total_ddr_size <= DDR_1024MB)\n> + *ddr_type = DDRTYPE_1024MB;\n> + else if (total_ddr_size <= DDR_2048MB)\n> + *ddr_type = DDRTYPE_2048MB;\n> + else if (total_ddr_size <= DDR_3072MB)\n> + *ddr_type = DDRTYPE_3072MB;\n> + else if (total_ddr_size <= DDR_4096MB)\n> + *ddr_type = DDRTYPE_4096MB;\n\nIf total_ddr_size > 4 GB, ddr_type remains 0. Is that intentional, or\nshould there be a final else clause for larger memory configurations?\n\n> diff --git a/arch/arm/mach-snapdragon/qcom_fit_multidtb.c b/arch/arm/mach-snapdragon/qcom_fit_multidtb.c\n> @@ -0,0 +1,1103 @@\n> + printf(\"DTB: %s\\n\", fdt_name);\n\nMaybe use log_info() here for consistency with the rest of the file?\n\nReviewed-by: Simon Glass \n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256\n header.s=google header.b=EEKkT9aj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org\n header.b=\"EEKkT9aj\";\n\tdkim-atps=neutral","phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=chromium.org","phobos.denx.de;\n spf=pass smtp.mailfrom=sjg@chromium.org"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzX4V49Dgz1yCv\n\tfor ; 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