[{"id":3680616,"web_url":"http://patchwork.ozlabs.org/comment/3680616/","msgid":"<395691b5-6361-45b8-b5f8-35f8fcf45fe1@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-22T13:07:15","subject":"Re: [PATCH] target/riscv: rvv: Handle mask/source overlap of vector\n reduction instructions","submitter":{"id":92288,"url":"http://patchwork.ozlabs.org/api/people/92288/","name":"Daniel Henrique Barboza","email":"daniel.barboza@oss.qualcomm.com"},"content":"On 4/17/2026 9:06 AM, Anton Blanchard wrote:\n> Masked vector reduction instructions must not use v0 as a source register.\n> Check rs1 and rs2 against the mask register when vm=0.\n> \n> Signed-off-by: Anton Blanchard \n> ---\n\nReviewed-by: Daniel Henrique Barboza \n\n> target/riscv/insn_trans/trans_rvv.c.inc | 2 ++\n> 1 file changed, 2 insertions(+)\n> \n> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\n> index d9a0027e0b..6e8d32636e 100644\n> --- a/target/riscv/insn_trans/trans_rvv.c.inc\n> +++ b/target/riscv/insn_trans/trans_rvv.c.inc\n> @@ -3046,6 +3046,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)\n> {\n> return require_rvv(s) &&\n> vext_check_isa_ill(s) &&\n> + require_vm(a->vm, a->rs1) &&\n> + require_vm(a->vm, a->rs2) &&\n> vext_check_reduction(s, a->rs2);\n> }\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ZB9HJzRH;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=PA+69jhT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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