[{"id":3678920,"web_url":"http://patchwork.ozlabs.org/comment/3678920/","msgid":"","list_archive_url":null,"date":"2026-04-18T00:10:34","subject":"Re: [PATCH v2 2/4] target/arm/cpu.h: New GPCCR fields","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/17/26 21:02, Jim MacArthur wrote:\n> Add SA, NSP, NA6, NA7 for GDI and GPCBW for good measure.\n> \n> Signed-off-by: Jim MacArthur \n> ---\n> target/arm/cpu.h | 5 +++++\n> 1 file changed, 5 insertions(+)\n\nReviewed-by: Richard Henderson \n\nr~\n\n> \n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 657ff4ab20..1cfef02dc0 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -2089,6 +2089,11 @@ FIELD(GPCCR, TBGPCD, 18, 1)\n> FIELD(GPCCR, NSO, 19, 1)\n> FIELD(GPCCR, L0GPTSZ, 20, 4)\n> FIELD(GPCCR, APPSAA, 24, 1)\n> +FIELD(GPCCR, SA, 25, 1)\n> +FIELD(GPCCR, NSP, 26, 1)\n> +FIELD(GPCCR, NA6, 27, 1)\n> +FIELD(GPCCR, NA7, 28, 1)\n> +FIELD(GPCCR, GPCBW, 29, 1)\n> \n> FIELD(MFAR, FPA, 12, 40)\n> FIELD(MFAR, NSE, 62, 1)\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ngBEoYTR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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