[{"id":3679604,"web_url":"http://patchwork.ozlabs.org/comment/3679604/","msgid":"<3d3eadbc-cb3a-48b6-95bf-e356c7e32600@linaro.org>","list_archive_url":null,"date":"2026-04-20T21:18:16","subject":"Re: [PATCH v6 2/4] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in\n Atomic LD/ST helpers","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/17/26 14:26, Philippe Mathieu-Daudé wrote:\n> Have callers set MO_ALIGN in the MemOp bits.\n> \n> Perform the access first, filling the TLB in the process.\n> If the tlb cannot be filled, access is not permitted, and\n> an exception is raised. Thus remove the now unnecessary\n> do_raise_exception() call.\n> \n> Since the TLB is filled, use probe_access() to get CP0_LLAddr.\n> \n> Move env->CP0_LLAddr and env->lladdr assignments so we\n> don't update them when an alignment fault occurs.\n> \n> Since we have a handy MemOpIdx, replace the legacy\n> cpu_ld*_mmuidx_ra() calls by cpu_ld*_mmu() equivalent.\n> \n> Suggested-by: Richard Henderson\n> Signed-off-by: Philippe Mathieu-Daudé\n> ---\n> target/mips/tcg/ldst_helper.c | 26 +++++++++++++++-----------\n> target/mips/tcg/translate.c | 2 +-\n> 2 files changed, 16 insertions(+), 12 deletions(-)\n\nReviewed-by: Richard Henderson \n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=k5veHi9Z;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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