[{"id":3678562,"web_url":"http://patchwork.ozlabs.org/comment/3678562/","msgid":"<23078bf0-838f-4a57-be8b-6ba2dd0a27d5@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-17T08:18:44","subject":"Re: [PATCH] PCI: qcom: Set max OPP before DBI access during resume","submitter":{"id":89450,"url":"http://patchwork.ozlabs.org/api/people/89450/","name":"Konrad Dybcio","email":"konrad.dybcio@oss.qualcomm.com"},"content":"On 4/17/26 6:16 AM, Qiang Yu wrote:\n> During resume, qcom_pcie_icc_opp_update() may access DBI registers before\n> the OPP votes are restored, which can trigger NoC errors.\n> \n> Set the PCIe controller to the maximum OPP first in resume_noirq(), then\n> proceed with link/DBI accesses. The OPP is later updated again based on\n> the actual link bandwidth requirements.\n> \n> Also introduce a small helper to reuse the max-OPP setup path shared with\n> probe.\n> \n> Fixes: 5b6272e0efd5 (\"PCI: qcom: Add OPP support to scale performance\")\n> Signed-off-by: Qiang Yu \n> ---\n> drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++++++++-------------\n> 1 file changed, 26 insertions(+), 16 deletions(-)\n> \n> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\n> index 9fdfc88ac15120b2b01cad746772ae612a2c9690..c9b201a1c033a9849e97db9ee4d07d26655d5a6c 100644\n> --- a/drivers/pci/controller/dwc/pcie-qcom.c\n> +++ b/drivers/pci/controller/dwc/pcie-qcom.c\n> @@ -1613,6 +1613,22 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)\n> \t}\n> }\n> \n> +static int qcom_pcie_set_max_opp(struct device *dev)\n\nCan this be a small non-zero vote instead?\n\nKonrad","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=jx8CbxBe;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=dDLvoHm9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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The OPP is later updated again based on\n> > the actual link bandwidth requirements.\n> > \n> > Also introduce a small helper to reuse the max-OPP setup path shared with\n> > probe.\n> > \n> > Fixes: 5b6272e0efd5 (\"PCI: qcom: Add OPP support to scale performance\")\n> > Signed-off-by: Qiang Yu \n> > ---\n> > drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++++++++-------------\n> > 1 file changed, 26 insertions(+), 16 deletions(-)\n> > \n> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\n> > index 9fdfc88ac15120b2b01cad746772ae612a2c9690..c9b201a1c033a9849e97db9ee4d07d26655d5a6c 100644\n> > --- a/drivers/pci/controller/dwc/pcie-qcom.c\n> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c\n> > @@ -1613,6 +1613,22 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)\n> > \t}\n> > }\n> > \n> > +static int qcom_pcie_set_max_opp(struct device *dev)\n> \n> Can this be a small non-zero vote instead?\n> \n\nIt won't make a difference. We are going to update the vote right after it.\nFurthermore, it will allow us to group the logic into one helper and call from\nboth probe() and resume().\n\n- Mani","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=GQ4yvM8x;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52706-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"GQ4yvM8x\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxqdw04nHz1yGt\n\tfor ; Fri, 17 Apr 2026 19:41:40 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 39F4E30C98EF\n\tfor ; Fri, 17 Apr 2026 09:32:56 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 83E7A3B6378;\n\tFri, 17 Apr 2026 09:30:37 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id EF5973B3893;\n\tFri, 17 Apr 2026 09:30:36 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 303EBC19425;\n\tFri, 17 Apr 2026 09:30:32 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776418237; cv=none;\n b=ABof8e/l5T0l1lFJwoIf9a5mJ8jI6T17aD5qsIyhGhnZYRPnmhAq0wMRjszDkE0YLaj27fmip5h94pyFJDsH6SfxNsh6mFeEUELpGItA7YhZm36AGBFHzsN1FBr/LSaPZ0jh7IfqnMesC1zefIQMBhV85MzSow4KBfAdAQRWPY4=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776418237; c=relaxed/simple;\n\tbh=OODs1MyWgSNpasOw1hA23+RBFDlFstERAlbq/6b8wFM=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=aCPv4e6tfEHTHkiGtOITszbg6Yb915McLvSFNdoKd+YDKyae8nFZ5Q2dXQPpsPFmDqwnzyi2Ie9y+xHS6js0qH2X+elyJjedDXOi+xzRBaGj7biW8LTimk6bu53uhBlIpuPKwxpjou2VRZIAQQPsQiVByBZdbv02Mhy9V4v8m88=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=GQ4yvM8x; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1776418236;\n\tbh=OODs1MyWgSNpasOw1hA23+RBFDlFstERAlbq/6b8wFM=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=GQ4yvM8xZuYo5PhUwW7XO6XulbcBvJxlhXl5LrlvIh/+8jcRKiL67KjYutgYM5uaU\n\t VszdfvA6AMmK+afpqvMNJE9X9WXuvqdoibKjoHhzWNezzqZAqJrwlKrBtY4rIMaotC\n\t o7MIGj71S0HF6oaAS62twx1qsb0/IORu2Bbvz0kuLBevRtNlQa7UuDTRnYhZEeSQiO\n\t Zf8yTncQxGk0yB61rWjeueGOYmme70h08ms00D0UGrTfV8O4i2PYP21zGlS3wpf597\n\t vAkMcStb88LoJ8tKUMK+Fz9npwFujSqiwtZAcQl0e4n2ov7s4PQ49uA5sC4JIm6QEK\n\t 75EQgr1j2LB2g==","Date":"Fri, 17 Apr 2026 15:00:29 +0530","From":"Manivannan Sadhasivam ","To":"Konrad Dybcio ","Cc":"Qiang Yu ,\n Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Rob Herring , Bjorn Helgaas ,\n Krishna chaitanya chundru ,\n linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org","Subject":"Re: [PATCH] PCI: qcom: Set max OPP before DBI access during resume","Message-ID":"","References":"<20260416-setmaxopp-v1-1-6a74e2d945a0@oss.qualcomm.com>\n <23078bf0-838f-4a57-be8b-6ba2dd0a27d5@oss.qualcomm.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<23078bf0-838f-4a57-be8b-6ba2dd0a27d5@oss.qualcomm.com>"}}]