[{"id":3678925,"web_url":"http://patchwork.ozlabs.org/comment/3678925/","msgid":"<108fd113-a8aa-4ad3-902a-0d956e0b9c1d@linaro.org>","list_archive_url":null,"date":"2026-04-18T00:19:54","subject":"Re: [PATCH v5 4/4] target/mips: Check alignment for microMIPS pre-R6\n LD/ST multiple","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/17/26 13:57, Philippe Mathieu-Daudé wrote:\n> Pre-REL6 microMIPS requires alignment while REL6 microMIPS does not.\n> Use @default_tcg_memop_mask in gen_ldst_multiple(), it is set to\n> MO_UNALN for REL6 but MO_ALIGN for pre-REL6.\n> \n> Fixes: 3c824109da0 (\"target-mips: microMIPS ASE support\")\n> Reported-by: Richard Henderson\n> Signed-off-by: Philippe Mathieu-Daudé\n> ---\n> Good enough until making it explicit in a decodetree conversion.\n> ---\n> target/mips/tcg/micromips_translate.c.inc | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n\nReviewed-by: Richard Henderson \n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CTcb4dpz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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