[{"id":3678397,"web_url":"http://patchwork.ozlabs.org/comment/3678397/","msgid":"","list_archive_url":null,"date":"2026-04-16T21:32:18","subject":"Re: [PATCH v5 8/9] hw/hexagon: Define hexagon \"virt\" machine","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 23:03, Brian Cain wrote:\n> From: Brian Cain \n> \n> Signed-off-by: Brian Cain \n> ---\n> configs/devices/hexagon-softmmu/default.mak | 1 +\n> configs/targets/hexagon-softmmu.mak | 1 +\n> include/hw/hexagon/virt.h | 43 ++\n> hw/hexagon/virt.c | 456 ++++++++++++++++++++\n> target/hexagon/cpu.c | 2 +\n> hw/hexagon/Kconfig | 10 +\n> hw/hexagon/meson.build | 2 +\n> tests/qemu-iotests/testenv.py | 1 +\n> 8 files changed, 516 insertions(+)\n> create mode 100644 include/hw/hexagon/virt.h\n> create mode 100644 hw/hexagon/virt.c\n> \n> diff --git a/configs/devices/hexagon-softmmu/default.mak b/configs/devices/hexagon-softmmu/default.mak\n> index 08e709aea72..37b4f9f3237 100644\n> --- a/configs/devices/hexagon-softmmu/default.mak\n> +++ b/configs/devices/hexagon-softmmu/default.mak\n> @@ -3,5 +3,6 @@\n> # Uncomment the following lines to disable these optional devices:\n> \n> # Boards are selected by default, uncomment to keep out of the build.\n> +# CONFIG_HEX_VIRT=y\n> # CONFIG_HEX_DSP=y\n> # CONFIG_L2VIC=y\n> diff --git a/configs/targets/hexagon-softmmu.mak b/configs/targets/hexagon-softmmu.mak\n> index fdfa29b4f39..a77c100f0c5 100644\n> --- a/configs/targets/hexagon-softmmu.mak\n> +++ b/configs/targets/hexagon-softmmu.mak\n> @@ -5,3 +5,4 @@ TARGET_XML_FILES=hexagon-core.xml hexagon-hvx.xml\n> TARGET_LONG_BITS=32\n> TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y\n> TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y\n> +TARGET_NEED_FDT=y\n> diff --git a/include/hw/hexagon/virt.h b/include/hw/hexagon/virt.h\n> new file mode 100644\n> index 00000000000..a54eac5cf00\n> --- /dev/null\n> +++ b/include/hw/hexagon/virt.h\n> @@ -0,0 +1,43 @@\n> +/*\n> + * Definitions for hexagon virt board.\n> + *\n> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#ifndef HW_HEXAGONVIRT_H\n> +#define HW_HEXAGONVIRT_H\n> +\n> +#include \"hw/core/boards.h\"\n> +#include \"target/hexagon/cpu.h\"\n> +\n> +struct HexagonVirtMachineState {\n> + /*< private >*/\n\n(remove this unuseful comment)\n\n> + MachineState parent_obj;\n> +\n> + int fdt_size;\n> + MemoryRegion *sys;\n> + MemoryRegion cfgtable;\n> + MemoryRegion ram;\n> + MemoryRegion tcm;\n> + MemoryRegion vtcm;\n> + MemoryRegion bios;\n> + DeviceState *l2vic;\n> + Clock *apb_clk;\n> +};\n> +\n> +void hexagon_load_fdt(const struct HexagonVirtMachineState *vms);\n> +\n> +enum {\n> + VIRT_UART0,\n> + VIRT_QTMR0,\n> + VIRT_QTMR1,\n> + VIRT_GPT,\n> + VIRT_MMIO,\n> + VIRT_FDT,\n> +};\n\nDo we really need to expose this enum? Otherwise it could go in the source.\n\n> +\n> +#define TYPE_HEXAGON_VIRT_MACHINE MACHINE_TYPE_NAME(\"virt\")\n> +OBJECT_DECLARE_SIMPLE_TYPE(HexagonVirtMachineState, HEXAGON_VIRT_MACHINE)\n> +\n> +#endif /* HW_HEXAGONVIRT_H */\n> diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c\n> new file mode 100644\n> index 00000000000..ff93b5221ba\n> --- /dev/null\n> +++ b/hw/hexagon/virt.c\n> @@ -0,0 +1,456 @@\n> +/*\n> + * Hexagon virt emulation\n> + *\n> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"qapi/error.h\"\n> +#include \"hw/hexagon/virt.h\"\n> +#include \"elf.h\"\n> +#include \"hw/char/pl011.h\"\n> +#include \"hw/core/clock.h\"\n> +#include \"hw/core/sysbus-fdt.h\"\n> +#include \"hw/hexagon/hexagon.h\"\n> +#include \"hw/hexagon/hexagon_globalreg.h\"\n> +#include \"hw/hexagon/hexagon_tlb.h\"\n> +#include \"hw/core/loader.h\"\n> +#include \"hw/core/qdev-properties.h\"\n> +#include \"hw/core/qdev-clock.h\"\n> +#include \"hw/core/register.h\"\n> +#include \"qemu/error-report.h\"\n> +#include \"qemu/guest-random.h\"\n> +#include \"qemu/units.h\"\n> +#include \"elf.h\"\n> +#include \"machine_cfg_v68n_1024.h.inc\"\n> +#include \"system/address-spaces.h\"\n> +#include \"system/device_tree.h\"\n> +#include \"system/reset.h\"\n> +#include \"system/system.h\"\n> +#include \n> +\n> +static const int VIRTIO_DEV_COUNT = 8;\n> +\n> +static const MemMapEntry base_memmap[] = {\n> + [VIRT_UART0] = { 0x10000000, 0x00000200 },\n> + [VIRT_MMIO] = { 0x11000000, 0x1000000, },\n> + [VIRT_GPT] = { 0xab000000, 0x00001000 },\n> + [VIRT_FDT] = { 0x99800000, 0x00400000 },\n> +};\n> +\n> +static const int irqmap[] = {\n> + [VIRT_MMIO] = 18, /* ...to 18 + VIRTIO_DEV_COUNT - 1 */\n> + [VIRT_GPT] = 12,\n> + [VIRT_UART0] = 15,\n> + [VIRT_QTMR0] = 2,\n> + [VIRT_QTMR1] = 4,\n> +};\n> +\n> +\n> +static void create_fdt(HexagonVirtMachineState *vms)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + void *fdt = create_device_tree(&vms->fdt_size);\n> + uint8_t rng_seed[32];\n> +\n> + if (!fdt) {\n> + error_report(\"create_device_tree() failed\");\n> + exit(1);\n> + }\n> +\n> + ms->fdt = fdt;\n> +\n> + qemu_fdt_setprop_cell(fdt, \"/\", \"#address-cells\", 0x2);\n> + qemu_fdt_setprop_cell(fdt, \"/\", \"#size-cells\", 0x1);\n> + qemu_fdt_setprop_string(fdt, \"/\", \"model\", \"hexagon-virt,qemu\");\n> + qemu_fdt_setprop_string(fdt, \"/\", \"compatible\", \"qcom,sm8150\");\n> +\n> + qemu_fdt_add_subnode(fdt, \"/soc\");\n> + qemu_fdt_setprop_cell(fdt, \"/soc\", \"#address-cells\", 0x2);\n> + qemu_fdt_setprop_cell(fdt, \"/soc\", \"#size-cells\", 0x1);\n> + qemu_fdt_setprop(fdt, \"/soc\", \"ranges\", NULL, 0);\n> +\n> + qemu_fdt_add_subnode(fdt, \"/chosen\");\n> + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));\n> + qemu_fdt_setprop(fdt, \"/chosen\", \"rng-seed\", rng_seed, sizeof(rng_seed));\n> +}\n> +\n> +static void fdt_add_hvx(HexagonVirtMachineState *vms,\n> + const struct hexagon_machine_config *m_cfg,\n> + Error **errp)\n> +{\n> + const MachineState *ms = MACHINE(vms);\n> + uint32_t vtcm_size_bytes = m_cfg->cfgtable.vtcm_size_kb * 1024;\n> + if (vtcm_size_bytes > 0) {\n> + memory_region_init_ram(&vms->vtcm, NULL, \"vtcm.ram\", vtcm_size_bytes,\n> + errp);\n> + memory_region_add_subregion(vms->sys, m_cfg->cfgtable.vtcm_base << 16,\n> + &vms->vtcm);\n> +\n> + qemu_fdt_add_subnode(ms->fdt, \"/soc/vtcm\");\n> + qemu_fdt_setprop_string(ms->fdt, \"/soc/vtcm\", \"compatible\",\n> + \"qcom,hexagon_vtcm\");\n> +\n> + assert(sizeof(m_cfg->cfgtable.vtcm_base) == sizeof(uint32_t));\n> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/vtcm\", \"reg\", 0,\n> + m_cfg->cfgtable.vtcm_base << 16,\n> + vtcm_size_bytes);\n> + }\n> +\n> + if (m_cfg->cfgtable.ext_contexts > 0) {\n> + qemu_fdt_add_subnode(ms->fdt, \"/soc/hvx\");\n> + qemu_fdt_setprop_string(ms->fdt, \"/soc/hvx\", \"compatible\",\n> + \"qcom,hexagon-hvx\");\n> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/hvx\", \"qcom,hvx-max-ctxts\",\n> + m_cfg->cfgtable.ext_contexts);\n> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/hvx\", \"qcom,hvx-vlength\",\n> + m_cfg->cfgtable.hvx_vec_log_length);\n> + }\n> +}\n> +\n> +static int32_t irq_hvm_ic_phandle = -1;\n\nMaybe better to pass these handles as pointer argument?\n\n> +static void fdt_add_hvm_pic_node(HexagonVirtMachineState *vms,\n> + const struct hexagon_machine_config *m_cfg)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + irq_hvm_ic_phandle = qemu_fdt_alloc_phandle(ms->fdt);\n> +\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc\", \"interrupt-parent\",\n> + irq_hvm_ic_phandle);\n> +\n> + qemu_fdt_add_subnode(ms->fdt, \"/soc/interrupt-controller\");\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc/interrupt-controller\",\n> + \"#address-cells\", 2);\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc/interrupt-controller\",\n> + \"#interrupt-cells\", 2);\n> + qemu_fdt_setprop_string(ms->fdt, \"/soc/interrupt-controller\", \"compatible\",\n> + \"qcom,h2-pic,hvm-pic\");\n> + qemu_fdt_setprop(ms->fdt, \"/soc/interrupt-controller\",\n> + \"interrupt-controller\", NULL, 0);\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc/interrupt-controller\", \"phandle\",\n> + irq_hvm_ic_phandle);\n> +\n> + sysbus_mmio_map(SYS_BUS_DEVICE(vms->l2vic), 1,\n> + m_cfg->cfgtable.fastl2vic_base << 16);\n> +}\n> +\n> +\n> +static void fdt_add_gpt_node(HexagonVirtMachineState *vms)\n> +{\n> + g_autofree char *name = NULL;\n> + MachineState *ms = MACHINE(vms);\n> +\n> + name = g_strdup_printf(\"/soc/gpt@%\" PRIx64,\n> + (int64_t)base_memmap[VIRT_GPT].base);\n> + qemu_fdt_add_subnode(ms->fdt, name);\n> + qemu_fdt_setprop_string(ms->fdt, name, \"compatible\",\n> + \"qcom,h2-timer,hvm-timer\");\n> + qemu_fdt_setprop_cells(ms->fdt, name, \"interrupts\", irqmap[VIRT_GPT], 0);\n> + qemu_fdt_setprop_cells(ms->fdt, name, \"reg\", 0x0,\n> + base_memmap[VIRT_GPT].base,\n> + base_memmap[VIRT_GPT].size);\n> +}\n> +\n> +static int32_t clock_phandle = -1;\n\n(ditto)\n\n> +static void fdt_add_clocks(const HexagonVirtMachineState *vms)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + clock_phandle = qemu_fdt_alloc_phandle(ms->fdt);\n> + qemu_fdt_add_subnode(ms->fdt, \"/apb-pclk\");\n> + qemu_fdt_setprop_string(ms->fdt, \"/apb-pclk\", \"compatible\", \"fixed-clock\");\n> + qemu_fdt_setprop_cell(ms->fdt, \"/apb-pclk\", \"#clock-cells\", 0x0);\n> + qemu_fdt_setprop_cell(ms->fdt, \"/apb-pclk\", \"clock-frequency\", 24000000);\n> + qemu_fdt_setprop_string(ms->fdt, \"/apb-pclk\", \"clock-output-names\",\n> + \"clk24mhz\");\n> + qemu_fdt_setprop_cell(ms->fdt, \"/apb-pclk\", \"phandle\", clock_phandle);\n> +}\n> +\n> +static void fdt_add_uart(const HexagonVirtMachineState *vms, int uart)\n> +{\n> + char *nodename;\n> + hwaddr base = base_memmap[uart].base;\n> + hwaddr size = base_memmap[uart].size;\n> + assert(uart == 0);\n> + int irq = irqmap[VIRT_UART0 + uart];\n> + const char compat[] = \"arm,pl011\\0arm,primecell\";\n> + const char clocknames[] = \"uartclk\\0apb_pclk\";\n> + MachineState *ms = MACHINE(vms);\n> + DeviceState *dev;\n> + SysBusDevice *s;\n> +\n> + dev = qdev_new(TYPE_PL011);\n> + s = SYS_BUS_DEVICE(dev);\n> + qdev_prop_set_chr(dev, \"chardev\", serial_hd(0));\n> + qdev_connect_clock_in(dev, \"clk\", vms->apb_clk);\n> + sysbus_realize_and_unref(s, &error_fatal);\n> + sysbus_mmio_map(s, 0, base);\n> + if (vms->l2vic) {\n> + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->l2vic, irq));\n> + }\n> +\n> + nodename = g_strdup_printf(\"/pl011@%\" PRIx64, base);\n> + qemu_fdt_add_subnode(ms->fdt, nodename);\n> +\n> + /* Note that we can't use setprop_string because of the embedded NUL */\n> + qemu_fdt_setprop(ms->fdt, nodename, \"compatible\", compat, sizeof(compat));\n> + qemu_fdt_setprop_cells(ms->fdt, nodename, \"reg\", 0, base, size);\n> + if (vms->l2vic) {\n> + qemu_fdt_setprop_cells(ms->fdt, nodename, \"interrupts\",\n> + 32 + irq, 0);\n> + qemu_fdt_setprop_cell(ms->fdt, nodename, \"interrupt-parent\",\n> + irq_hvm_ic_phandle);\n> + }\n> + qemu_fdt_setprop_cells(ms->fdt, nodename, \"clocks\", clock_phandle,\n> + clock_phandle);\n> + qemu_fdt_setprop(ms->fdt, nodename, \"clock-names\", clocknames,\n> + sizeof(clocknames));\n> +\n> + qemu_fdt_setprop_string(ms->fdt, \"/chosen\", \"stdout-path\", nodename);\n> + qemu_fdt_add_subnode(ms->fdt, \"/aliases\");\n> + qemu_fdt_setprop_string(ms->fdt, \"/aliases\", \"serial0\", nodename);\n> +\n> + g_free(nodename);\n> +}\n> +\n> +static void fdt_add_cpu_nodes(const HexagonVirtMachineState *vms)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + qemu_fdt_add_subnode(ms->fdt, \"/cpus\");\n> + qemu_fdt_setprop_cell(ms->fdt, \"/cpus\", \"#address-cells\", 0x1);\n> + qemu_fdt_setprop_cell(ms->fdt, \"/cpus\", \"#size-cells\", 0x0);\n> +\n> + /* cpu nodes */\n> + for (int num = ms->smp.cpus - 1; num >= 0; num--) {\n> + char *nodename = g_strdup_printf(\"/cpus/cpu@%d\", num);\n> + qemu_fdt_add_subnode(ms->fdt, nodename);\n> + qemu_fdt_setprop_string(ms->fdt, nodename, \"device_type\", \"cpu\");\n> + qemu_fdt_setprop_cell(ms->fdt, nodename, \"reg\", num);\n> + qemu_fdt_setprop_cell(ms->fdt, nodename, \"phandle\",\n> + qemu_fdt_alloc_phandle(ms->fdt));\n> + g_free(nodename);\n> + }\n> +}\n> +\n> +\n> +static void fdt_add_virtio_devices(const HexagonVirtMachineState *vms)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + /* VirtIO MMIO devices */\n> + for (int i = 0; i < VIRTIO_DEV_COUNT; i++) {\n> + char *nodename;\n> + int irq = irqmap[VIRT_MMIO] + i;\n> + size_t size = base_memmap[VIRT_MMIO].size;\n> + hwaddr base = base_memmap[VIRT_MMIO].base + i * size;\n> +\n> + nodename = g_strdup_printf(\"/virtio_mmio@%\" PRIx64, base);\n> + qemu_fdt_add_subnode(ms->fdt, nodename);\n> + qemu_fdt_setprop_string(ms->fdt, nodename, \"compatible\", \"virtio,mmio\");\n> + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, \"reg\", 2, base, 1,\n> + size);\n> + qemu_fdt_setprop_cells(ms->fdt, nodename, \"interrupts\", irq, 0);\n> + qemu_fdt_setprop_cell(ms->fdt, nodename, \"interrupt-parent\",\n> + irq_hvm_ic_phandle);\n> +\n> + sysbus_create_simple(\n> + \"virtio-mmio\", base,\n> + qdev_get_gpio_in(vms->l2vic, irqmap[VIRT_MMIO] + i));\n> +\n> + g_free(nodename);\n> + }\n> +}\n> +\n> +static void virt_instance_init(Object *obj)\n> +{\n> + HexagonVirtMachineState *vms = HEXAGON_VIRT_MACHINE(obj);\n> +\n> + create_fdt(vms);\n> +}\n> +\n> +void hexagon_load_fdt(const HexagonVirtMachineState *vms)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + hwaddr fdt_addr = base_memmap[VIRT_FDT].base;\n> + uint32_t fdtsize = vms->fdt_size;\n> +\n> + g_assert(fdtsize <= base_memmap[VIRT_FDT].size);\n> + /* copy in the device tree */\n> + rom_add_blob_fixed_as(\"fdt\", ms->fdt, fdtsize, fdt_addr,\n> + &address_space_memory);\n> + qemu_register_reset_nosnapshotload(\n> + qemu_fdt_randomize_seeds,\n> + rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));\n> +}\n> +\n> +static uint64_t load_kernel(const HexagonVirtMachineState *vms)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + uint64_t entry = 0;\n> + if (load_elf_ram_sym(ms->kernel_filename, NULL, NULL, NULL, &entry, NULL,\n> + NULL, NULL, 0, EM_HEXAGON, 0, 0, &address_space_memory,\n> + false, NULL) > 0) {\n> + return entry;\n> + }\n> + error_report(\"error loading '%s'\", ms->kernel_filename);\n> + exit(1);\n> +}\n> +\n> +static uint64_t load_bios(HexagonVirtMachineState *vms)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + uint64_t bios_addr = 0x0; /* Load BIOS at reset vector address 0x0 */\n> + int bios_size;\n> +\n> + bios_size = load_image_targphys(ms->firmware ?: \"\",\n> + bios_addr, 64 * 1024, NULL);\n> + if (bios_size < 0) {\n> + error_report(\"Could not load BIOS '%s'\", ms->firmware ?: \"\");\n> + exit(1);\n> + }\n> +\n> + return bios_addr; /* Return entry point at address 0x0 */\n> +}\n> +\n> +static void do_cpu_reset(void *opaque)\n> +{\n> + HexagonCPU *cpu = opaque;\n> + CPUState *cs = CPU(cpu);\n> + cpu_reset(cs);\n> +}\n> +\n> +static void virt_init(MachineState *ms)\n> +{\n> + HexagonVirtMachineState *vms = HEXAGON_VIRT_MACHINE(ms);\n> + const struct hexagon_machine_config *m_cfg = &v68n_1024;\n> + const char *cpu_model;\n> + DeviceState *gsregs_dev;\n> + DeviceState *tlb_dev;\n> + HexagonCPU *cpu_0;\n\nMaybe directly to only use a single cast:\n\n DeviceState *cpu0;\n\n> +\n> + qemu_fdt_setprop_string(ms->fdt, \"/chosen\", \"bootargs\", ms->kernel_cmdline);\n> +\n> + vms->sys = get_system_memory();\n> +\n> + /* Create APB clock for peripherals */\n> + vms->apb_clk = clock_new(OBJECT(ms), \"apb-pclk\");\n> + clock_set_hz(vms->apb_clk, 24000000);\n> +\n> + memory_region_init_ram(&vms->ram, NULL, \"ddr.ram\", ms->ram_size,\n> + &error_fatal);\n> + memory_region_add_subregion(vms->sys, 0x0, &vms->ram);\n> +\n> + if (m_cfg->l2tcm_size) {\n> + memory_region_init_ram(&vms->tcm, NULL, \"tcm.ram\", m_cfg->l2tcm_size,\n> + &error_fatal);\n> + memory_region_add_subregion(vms->sys, m_cfg->cfgtable.l2tcm_base << 16,\n> + &vms->tcm);\n> + }\n> +\n> + memory_region_init_rom(&vms->cfgtable, NULL, \"config_table.rom\",\n> + sizeof(m_cfg->cfgtable), &error_fatal);\n> + memory_region_add_subregion(vms->sys, m_cfg->cfgbase, &vms->cfgtable);\n> + fdt_add_hvx(vms, m_cfg, &error_fatal);\n> + cpu_model = ms->cpu_type;\n> +\n> + if (!cpu_model) {\n> + cpu_model = HEXAGON_CPU_TYPE_NAME(\"v68\");\n\nCan that happen? There is a default defined...\n\n> + }\n> +\n> + gsregs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);\n> + object_property_add_child(OBJECT(ms), \"global-regs\", OBJECT(gsregs_dev));\n> + qdev_prop_set_uint64(gsregs_dev, \"config-table-addr\", m_cfg->cfgbase);\n> + qdev_prop_set_uint32(gsregs_dev, \"dsp-rev\", v68_rev);\n> + sysbus_realize_and_unref(SYS_BUS_DEVICE(gsregs_dev), &error_fatal);\n> +\n> + tlb_dev = qdev_new(TYPE_HEXAGON_TLB);\n\nWhere is hw/hexagon/hexagon_tlb.h?\n\n> + object_property_add_child(OBJECT(ms), \"tlb\", OBJECT(tlb_dev));\n> + qdev_prop_set_uint32(tlb_dev, \"num-entries\",\n> + m_cfg->cfgtable.jtlb_size_entries);\n> + sysbus_realize_and_unref(SYS_BUS_DEVICE(tlb_dev), &error_fatal);\n> +\n> + cpu_0 = NULL;\n> + for (int i = 0; i < ms->smp.cpus; i++) {\n\nI suppose they belong to a cluster. In the future we'd create\nthem within a TYPE_CPU_CLUSTER.\n\n> + HexagonCPU *cpu = HEXAGON_CPU(object_new(ms->cpu_type));\n> + qemu_register_reset(do_cpu_reset, cpu);\n> +\n> + if (i == 0) {\n> + cpu_0 = cpu;\n> + if (ms->kernel_filename) {\n> + uint64_t entry = load_kernel(vms);\n> + qdev_prop_set_uint32(DEVICE(cpu_0), \"exec-start-addr\", entry);\n> + } else if (ms->firmware) {\n> + uint64_t entry = load_bios(vms);\n> + qdev_prop_set_uint32(DEVICE(cpu_0), \"exec-start-addr\", entry);\n> + }\n> + }\n> + qdev_prop_set_uint32(DEVICE(cpu), \"htid\", i);\n> + qdev_prop_set_bit(DEVICE(cpu), \"start-powered-off\", (i != 0));\n> + object_property_set_link(OBJECT(cpu), \"global-regs\",\n> + OBJECT(gsregs_dev), &error_fatal);\n> + object_property_set_link(OBJECT(cpu), \"tlb\",\n> + OBJECT(tlb_dev), &error_fatal);\n> +\n> + if (!qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal)) {\n> + return;\n> + }\n> + }\n> + /* TODO: enable l2vic when l2vic device arrives */\n> + if (object_class_by_name(\"l2vic\")) {\n> + vms->l2vic = sysbus_create_varargs(\n> + \"l2vic\", m_cfg->l2vic_base,\n> + qdev_get_gpio_in(DEVICE(cpu_0), 0),\n> + qdev_get_gpio_in(DEVICE(cpu_0), 1),\n> + qdev_get_gpio_in(DEVICE(cpu_0), 2),\n> + qdev_get_gpio_in(DEVICE(cpu_0), 3),\n> + qdev_get_gpio_in(DEVICE(cpu_0), 4),\n> + qdev_get_gpio_in(DEVICE(cpu_0), 5),\n> + qdev_get_gpio_in(DEVICE(cpu_0), 6),\n> + qdev_get_gpio_in(DEVICE(cpu_0), 7), NULL);\n> +\n> + fdt_add_hvm_pic_node(vms, m_cfg);\n> + fdt_add_virtio_devices(vms);\n> + fdt_add_gpt_node(vms);\n> + }\n> +\n> + fdt_add_cpu_nodes(vms);\n> + fdt_add_clocks(vms);\n> + fdt_add_uart(vms, VIRT_UART0);\n> +\n> + rom_add_blob_fixed_as(\"config_table.rom\", &m_cfg->cfgtable,\n> + sizeof(m_cfg->cfgtable), m_cfg->cfgbase,\n> + &address_space_memory);\n> +\n> +\n> + hexagon_load_fdt(vms);\n> +}\n> +\n> +\n> +static void virt_class_init(ObjectClass *oc, const void *data)\n> +{\n> + MachineClass *mc = MACHINE_CLASS(oc);\n> +\n> + mc->desc = \"Hexagon Virtual Machine\";\n> + mc->init = virt_init;\n> + mc->default_cpu_type = HEXAGON_CPU_TYPE_NAME(\"v68\");\n\n(this is the default CPU type)\n\n> + mc->default_ram_size = 4 * GiB;\n> + mc->max_cpus = 8;\n> + mc->default_cpus = 8;\n> + mc->is_default = false;\n> + mc->default_kernel_irqchip_split = false;\n> + mc->block_default_type = IF_VIRTIO;\n> + mc->default_boot_order = NULL;\n> + mc->no_cdrom = 1;\n> + mc->numa_mem_supported = false;\n> + mc->default_nic = \"virtio-mmio-bus\";\n> +}\n> +\n> +\n> +static const TypeInfo virt_machine_types[] = { {\n> + .name = TYPE_HEXAGON_VIRT_MACHINE,\n> + .parent = TYPE_MACHINE,\n> + .instance_size = sizeof(HexagonVirtMachineState),\n> + .class_init = virt_class_init,\n> + .instance_init = virt_instance_init,\n> +} };\n> +\n> +DEFINE_TYPES(virt_machine_types)\n> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\n> index 355abb4fd24..01781a76caf 100644\n> --- a/target/hexagon/cpu.c\n> +++ b/target/hexagon/cpu.c\n> @@ -68,6 +68,8 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n> \n> static const Property hexagon_cpu_properties[] = {\n> #if !defined(CONFIG_USER_ONLY)\n> + DEFINE_PROP_LINK(\"tlb\", HexagonCPU, tlb, TYPE_HEXAGON_TLB,\n> + HexagonTLBState *),\n> DEFINE_PROP_UINT32(\"exec-start-addr\", HexagonCPU, boot_addr, 0xffffffff),\n> DEFINE_PROP_LINK(\"global-regs\", HexagonCPU, globalregs,\n> TYPE_HEXAGON_GLOBALREG, HexagonGlobalRegState *),\n> diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig\n> index cdf7770a305..52065ab3b22 100644\n> --- a/hw/hexagon/Kconfig\n> +++ b/hw/hexagon/Kconfig\n> @@ -2,3 +2,13 @@ config HEX_DSP\n> bool\n> default y\n> depends on HEXAGON\n> +\n> +config HEX_VIRT\n> + bool\n> + default y\n> + depends on HEX_DSP && FDT\n> + select DEVICE_TREE\n> + select VIRTIO_MMIO\n> + select PL011\n> + select VIRTIO_BLK\n> + select VIRTIO_SCSI\n> diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build\n> index f528d2bc4ab..5b6a5e11a17 100644\n> --- a/hw/hexagon/meson.build\n> +++ b/hw/hexagon/meson.build\n> @@ -4,3 +4,5 @@ hexagon_ss.add(files('hexagon_globalreg.c'))\n> hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c'))\n> \n> hw_arch += {'hexagon': hexagon_ss}\n> +\n> +hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c'))\n> diff --git a/tests/qemu-iotests/testenv.py b/tests/qemu-iotests/testenv.py\n> index c357e6ebf50..86bcdf7cfad 100644\n> --- a/tests/qemu-iotests/testenv.py\n> +++ b/tests/qemu-iotests/testenv.py\n> @@ -259,6 +259,7 @@ def __init__(self, source_dir: str, build_dir: str,\n> ('arm', 'virt'),\n> ('aarch64', 'virt'),\n> ('avr', 'mega2560'),\n> + ('hexagon', 'virt'),\n> ('m68k', 'virt'),\n> ('or1k', 'virt'),\n> ('riscv32', 'virt'),","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org 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<20260416210305.2255579-9-brian.cain@oss.qualcomm.com>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","In-Reply-To":"<20260416210305.2255579-9-brian.cain@oss.qualcomm.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::330;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678487,"web_url":"http://patchwork.ozlabs.org/comment/3678487/","msgid":"<649073ae-7135-47df-a3d7-fd032b1a5fc1@linaro.org>","list_archive_url":null,"date":"2026-04-17T05:47:55","subject":"Re: [PATCH v5 8/9] hw/hexagon: Define hexagon \"virt\" machine","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 23:32, Philippe Mathieu-Daudé wrote:\n> On 16/4/26 23:03, Brian Cain wrote:\n>> From: Brian Cain \n>>\n>> Signed-off-by: Brian Cain \n>> ---\n>>   configs/devices/hexagon-softmmu/default.mak |   1 +\n>>   configs/targets/hexagon-softmmu.mak         |   1 +\n>>   include/hw/hexagon/virt.h                   |  43 ++\n>>   hw/hexagon/virt.c                           | 456 ++++++++++++++++++++\n>>   target/hexagon/cpu.c                        |   2 +\n>>   hw/hexagon/Kconfig                          |  10 +\n>>   hw/hexagon/meson.build                      |   2 +\n>>   tests/qemu-iotests/testenv.py               |   1 +\n>>   8 files changed, 516 insertions(+)\n>>   create mode 100644 include/hw/hexagon/virt.h\n>>   create mode 100644 hw/hexagon/virt.c\n\n\n>> +    gsregs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);\n>> +    object_property_add_child(OBJECT(ms), \"global-regs\", \n>> OBJECT(gsregs_dev));\n>> +    qdev_prop_set_uint64(gsregs_dev, \"config-table-addr\", m_cfg- \n>> >cfgbase);\n>> +    qdev_prop_set_uint32(gsregs_dev, \"dsp-rev\", v68_rev);\n>> +    sysbus_realize_and_unref(SYS_BUS_DEVICE(gsregs_dev), &error_fatal);\n>> +\n>> +    tlb_dev = qdev_new(TYPE_HEXAGON_TLB);\n> \n> Where is hw/hexagon/hexagon_tlb.h?\n\nFound it in \"part 1/3\":\n\nhttps://lore.kernel.org/qemu-devel/20260401152657.314902-35-brian.cain@oss.qualcomm.com/\n\n> \n>> +    object_property_add_child(OBJECT(ms), \"tlb\", OBJECT(tlb_dev));\n>> +    qdev_prop_set_uint32(tlb_dev, \"num-entries\",\n>> +                         m_cfg->cfgtable.jtlb_size_entries);\n>> +    sysbus_realize_and_unref(SYS_BUS_DEVICE(tlb_dev), &error_fatal);","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=k+2doz6d;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No 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hexagon \"virt\" machine","Content-Language":"en-US","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"Brian Cain , qemu-devel@nongnu.org","Cc":"ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com,\n marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com,\n sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng,\n pierrick.bouvier@oss.qualcomm.com, Brian Cain ,\n Paolo Bonzini , Kevin Wolf ,\n Hanna Reitz ,\n \"open list:Block layer core\" ","References":"<20260416210305.2255579-1-brian.cain@oss.qualcomm.com>\n <20260416210305.2255579-9-brian.cain@oss.qualcomm.com>\n ","In-Reply-To":"","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3679432,"web_url":"http://patchwork.ozlabs.org/comment/3679432/","msgid":"<20260420145536.1198387-1-matheus.bernardino@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-20T14:55:36","subject":"Re: [PATCH v5 8/9] hw/hexagon: Define hexagon \"virt\" machine","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/people/90606/","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"content":"On Thu, 16 Apr 2026 14:03:04 -0700 Brian Cain wrote:\n>\n> diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c\n> new file mode 100644\n> index 00000000000..ff93b5221ba\n> --- /dev/null\n> +++ b/hw/hexagon/virt.c\n> @@ -0,0 +1,456 @@\n> +/*\n> + * Hexagon virt emulation\n> + *\n> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"qapi/error.h\"\n> +#include \"hw/hexagon/virt.h\"\n> +#include \"elf.h\"\n> +#include \"hw/char/pl011.h\"\n> +#include \"hw/core/clock.h\"\n> +#include \"hw/core/sysbus-fdt.h\"\n> +#include \"hw/hexagon/hexagon.h\"\n> +#include \"hw/hexagon/hexagon_globalreg.h\"\n> +#include \"hw/hexagon/hexagon_tlb.h\"\n> +#include \"hw/core/loader.h\"\n> +#include \"hw/core/qdev-properties.h\"\n> +#include \"hw/core/qdev-clock.h\"\n> +#include \"hw/core/register.h\"\n> +#include \"qemu/error-report.h\"\n> +#include \"qemu/guest-random.h\"\n> +#include \"qemu/units.h\"\n> +#include \"elf.h\"\n\nnit: elf.h was already included above\n\n> +#include \"machine_cfg_v68n_1024.h.inc\"\n> +#include \"system/address-spaces.h\"\n> +#include \"system/device_tree.h\"\n> +#include \"system/reset.h\"\n> +#include \"system/system.h\"\n> +#include \n> +\n[...]\n> +static void fdt_add_hvx(HexagonVirtMachineState *vms,\n> + const struct hexagon_machine_config *m_cfg,\n> + Error **errp)\n> +{\n> + const MachineState *ms = MACHINE(vms);\n> + uint32_t vtcm_size_bytes = m_cfg->cfgtable.vtcm_size_kb * 1024;\n> + if (vtcm_size_bytes > 0) {\n> + memory_region_init_ram(&vms->vtcm, NULL, \"vtcm.ram\", vtcm_size_bytes,\n> + errp);\n\nI was going to ask whether we should handle errp here and abort earlier, but\nfdt_add_hvx is always called with error_fatal, so that's fine. (I wonder, though,\nshould we remove \"Error **errp\" from the function signature and use error_abort\nhere directly, for clarity and future-proof?)\n\n> + memory_region_add_subregion(vms->sys, m_cfg->cfgtable.vtcm_base << 16,\n> + &vms->vtcm);\n> +\n> + qemu_fdt_add_subnode(ms->fdt, \"/soc/vtcm\");\n> + qemu_fdt_setprop_string(ms->fdt, \"/soc/vtcm\", \"compatible\",\n> + \"qcom,hexagon_vtcm\");\n> +\n> + assert(sizeof(m_cfg->cfgtable.vtcm_base) == sizeof(uint32_t));\n> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/vtcm\", \"reg\", 0,\n> + m_cfg->cfgtable.vtcm_base << 16,\n> + vtcm_size_bytes);\n> + }\n> +\n> + if (m_cfg->cfgtable.ext_contexts > 0) {\n> + qemu_fdt_add_subnode(ms->fdt, \"/soc/hvx\");\n> + qemu_fdt_setprop_string(ms->fdt, \"/soc/hvx\", \"compatible\",\n> + \"qcom,hexagon-hvx\");\n> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/hvx\", \"qcom,hvx-max-ctxts\",\n> + m_cfg->cfgtable.ext_contexts);\n> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/hvx\", \"qcom,hvx-vlength\",\n> + m_cfg->cfgtable.hvx_vec_log_length);\n> + }\n> +}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=HLaQiydq;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=hd8vTXzV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3680082,"web_url":"http://patchwork.ozlabs.org/comment/3680082/","msgid":"<3a88f4f4-01c5-4db4-ac0e-0d9b76fa86b9@linaro.org>","list_archive_url":null,"date":"2026-04-21T22:05:29","subject":"Re: [PATCH v5 8/9] hw/hexagon: Define hexagon \"virt\" machine","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 20/4/26 16:55, Matheus Tavares Bernardino wrote:\n> On Thu, 16 Apr 2026 14:03:04 -0700 Brian Cain wrote:\n>>\n>> diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c\n>> new file mode 100644\n>> index 00000000000..ff93b5221ba\n>> --- /dev/null\n>> +++ b/hw/hexagon/virt.c\n>> @@ -0,0 +1,456 @@\n>> +/*\n>> + * Hexagon virt emulation\n>> + *\n>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n>> + * SPDX-License-Identifier: GPL-2.0-or-later\n>> + */\n>> +\n>> +#include \"qemu/osdep.h\"\n>> +#include \"qapi/error.h\"\n>> +#include \"hw/hexagon/virt.h\"\n>> +#include \"elf.h\"\n>> +#include \"hw/char/pl011.h\"\n>> +#include \"hw/core/clock.h\"\n>> +#include \"hw/core/sysbus-fdt.h\"\n>> +#include \"hw/hexagon/hexagon.h\"\n>> +#include \"hw/hexagon/hexagon_globalreg.h\"\n>> +#include \"hw/hexagon/hexagon_tlb.h\"\n>> +#include \"hw/core/loader.h\"\n>> +#include \"hw/core/qdev-properties.h\"\n>> +#include \"hw/core/qdev-clock.h\"\n>> +#include \"hw/core/register.h\"\n>> +#include \"qemu/error-report.h\"\n>> +#include \"qemu/guest-random.h\"\n>> +#include \"qemu/units.h\"\n>> +#include \"elf.h\"\n> \n> nit: elf.h was already included above\n> \n>> +#include \"machine_cfg_v68n_1024.h.inc\"\n>> +#include \"system/address-spaces.h\"\n>> +#include \"system/device_tree.h\"\n>> +#include \"system/reset.h\"\n>> +#include \"system/system.h\"\n>> +#include \n>> +\n> [...]\n>> +static void fdt_add_hvx(HexagonVirtMachineState *vms,\n>> + const struct hexagon_machine_config *m_cfg,\n>> + Error **errp)\n>> +{\n>> + const MachineState *ms = MACHINE(vms);\n>> + uint32_t vtcm_size_bytes = m_cfg->cfgtable.vtcm_size_kb * 1024;\n>> + if (vtcm_size_bytes > 0) {\n>> + memory_region_init_ram(&vms->vtcm, NULL, \"vtcm.ram\", vtcm_size_bytes,\n>> + errp);\n> \n> I was going to ask whether we should handle errp here and abort earlier, but\n> fdt_add_hvx is always called with error_fatal, so that's fine. (I wonder, though,\n> should we remove \"Error **errp\" from the function signature and use error_abort\n> here directly, for clarity and future-proof?)\n\nThe current \"unchecked &errp because single use in function\" isn't\ngreat because we could easily add a 2nd use (like another\nmemory_region_init_ram call) and overwrite the first &errp, ignoring\nerrors. So with that in mind your suggestion is better IMO.\n\n> \n>> + memory_region_add_subregion(vms->sys, m_cfg->cfgtable.vtcm_base << 16,\n>> + &vms->vtcm);\n>> +\n>> + qemu_fdt_add_subnode(ms->fdt, \"/soc/vtcm\");\n>> + qemu_fdt_setprop_string(ms->fdt, \"/soc/vtcm\", \"compatible\",\n>> + \"qcom,hexagon_vtcm\");\n>> +\n>> + assert(sizeof(m_cfg->cfgtable.vtcm_base) == sizeof(uint32_t));\n>> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/vtcm\", \"reg\", 0,\n>> + m_cfg->cfgtable.vtcm_base << 16,\n>> + vtcm_size_bytes);\n>> + }\n>> +\n>> + if (m_cfg->cfgtable.ext_contexts > 0) {\n>> + qemu_fdt_add_subnode(ms->fdt, \"/soc/hvx\");\n>> + qemu_fdt_setprop_string(ms->fdt, \"/soc/hvx\", \"compatible\",\n>> + \"qcom,hexagon-hvx\");\n>> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/hvx\", \"qcom,hvx-max-ctxts\",\n>> + m_cfg->cfgtable.ext_contexts);\n>> + qemu_fdt_setprop_cells(ms->fdt, \"/soc/hvx\", \"qcom,hvx-vlength\",\n>> + m_cfg->cfgtable.hvx_vec_log_length);\n>> + }\n>> +}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TiQxZYl8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42d;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3680085,"web_url":"http://patchwork.ozlabs.org/comment/3680085/","msgid":"<62ff0065-b504-4f2c-93ef-745d00326e52@linaro.org>","list_archive_url":null,"date":"2026-04-21T22:10:27","subject":"Re: [PATCH v5 8/9] hw/hexagon: Define hexagon \"virt\" machine","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 23:03, Brian Cain wrote:\n> From: Brian Cain \n> \n> Signed-off-by: Brian Cain \n> ---\n> configs/devices/hexagon-softmmu/default.mak | 1 +\n> configs/targets/hexagon-softmmu.mak | 1 +\n> include/hw/hexagon/virt.h | 43 ++\n> hw/hexagon/virt.c | 456 ++++++++++++++++++++\n> target/hexagon/cpu.c | 2 +\n> hw/hexagon/Kconfig | 10 +\n> hw/hexagon/meson.build | 2 +\n> tests/qemu-iotests/testenv.py | 1 +\n> 8 files changed, 516 insertions(+)\n> create mode 100644 include/hw/hexagon/virt.h\n> create mode 100644 hw/hexagon/virt.c\n\n\n> diff --git a/include/hw/hexagon/virt.h b/include/hw/hexagon/virt.h\n> new file mode 100644\n> index 00000000000..a54eac5cf00\n> --- /dev/null\n> +++ b/include/hw/hexagon/virt.h\n> @@ -0,0 +1,43 @@\n> +/*\n> + * Definitions for hexagon virt board.\n> + *\n> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#ifndef HW_HEXAGONVIRT_H\n> +#define HW_HEXAGONVIRT_H\n> +\n> +#include \"hw/core/boards.h\"\n> +#include \"target/hexagon/cpu.h\"\n> +\n> +struct HexagonVirtMachineState {\n> + /*< private >*/\n> + MachineState parent_obj;\n> +\n> + int fdt_size;\n> + MemoryRegion *sys;\n> + MemoryRegion cfgtable;\n> + MemoryRegion ram;\n> + MemoryRegion tcm;\n> + MemoryRegion vtcm;\n> + MemoryRegion bios;\n> + DeviceState *l2vic;\n> + Clock *apb_clk;\n> +};\n\n\n> +#define TYPE_HEXAGON_VIRT_MACHINE MACHINE_TYPE_NAME(\"virt\")\n> +OBJECT_DECLARE_SIMPLE_TYPE(HexagonVirtMachineState, HEXAGON_VIRT_MACHINE)\n> +\n> +#endif /* HW_HEXAGONVIRT_H */\n> diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c\n> new file mode 100644\n> index 00000000000..ff93b5221ba\n> --- /dev/null\n> +++ b/hw/hexagon/virt.c\n\n\n> +static int32_t irq_hvm_ic_phandle = -1;\n\nWhy not store in HexagonVirtMachineState?\n\n> +static void fdt_add_hvm_pic_node(HexagonVirtMachineState *vms,\n> + const struct hexagon_machine_config *m_cfg)\n> +{\n> + MachineState *ms = MACHINE(vms);\n> + irq_hvm_ic_phandle = qemu_fdt_alloc_phandle(ms->fdt);\n> +\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc\", \"interrupt-parent\",\n> + irq_hvm_ic_phandle);\n> +\n> + qemu_fdt_add_subnode(ms->fdt, \"/soc/interrupt-controller\");\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc/interrupt-controller\",\n> + \"#address-cells\", 2);\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc/interrupt-controller\",\n> + \"#interrupt-cells\", 2);\n> + qemu_fdt_setprop_string(ms->fdt, \"/soc/interrupt-controller\", \"compatible\",\n> + \"qcom,h2-pic,hvm-pic\");\n> + qemu_fdt_setprop(ms->fdt, \"/soc/interrupt-controller\",\n> + \"interrupt-controller\", NULL, 0);\n> + qemu_fdt_setprop_cell(ms->fdt, \"/soc/interrupt-controller\", \"phandle\",\n> + irq_hvm_ic_phandle);\n> +\n> + sysbus_mmio_map(SYS_BUS_DEVICE(vms->l2vic), 1,\n> + m_cfg->cfgtable.fastl2vic_base << 16);\n> +}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TEXpB1mS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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