[{"id":3679479,"web_url":"http://patchwork.ozlabs.org/comment/3679479/","msgid":"<4e02874b-214b-406f-97b2-af7b78368a7e@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-20T16:57:58","subject":"Re: [PATCH v5 3/9] hw/hexagon: Add machine configs for sysemu","submitter":{"id":93152,"url":"http://patchwork.ozlabs.org/api/people/93152/","name":"Pierrick Bouvier","email":"pierrick.bouvier@oss.qualcomm.com"},"content":"On 4/16/2026 2:02 PM, Brian Cain wrote:\n> From: Brian Cain \n> \n> Some header includes are modified here: these are uniquely required for\n> basic system emulation functionality and had not been required for linux-user.\n> \n> Acked-by: Markus Armbruster \n> Co-authored-by: Mike Lambert \n> Co-authored-by: Sid Manning \n> Signed-off-by: Brian Cain \n> ---\n> MAINTAINERS | 2 +\n> include/hw/hexagon/hexagon.h | 150 +++++++++++++++++++++++\n> hw/hexagon/machine_cfg_v66g_1024.h.inc | 64 ++++++++++\n> hw/hexagon/hexagon_dsp.c | 161 +++++++++++++++++++++++++\n> system/qdev-monitor.c | 2 +-\n> target/hexagon/translate.c | 1 +\n> hw/Kconfig | 1 +\n> hw/hexagon/Kconfig | 4 +\n> hw/hexagon/meson.build | 6 +\n> hw/meson.build | 1 +\n> 10 files changed, 391 insertions(+), 1 deletion(-)\n> create mode 100644 include/hw/hexagon/hexagon.h\n> create mode 100644 hw/hexagon/machine_cfg_v66g_1024.h.inc\n> create mode 100644 hw/hexagon/hexagon_dsp.c\n> create mode 100644 hw/hexagon/Kconfig\n> create mode 100644 hw/hexagon/meson.build\n> \n\nReviewed-by: Pierrick Bouvier ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=F3BIZDek;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google 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,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= ","References":"<20260416210305.2255579-1-brian.cain@oss.qualcomm.com>\n <20260416210305.2255579-4-brian.cain@oss.qualcomm.com>","From":"Pierrick Bouvier ","Content-Language":"en-US","In-Reply-To":"<20260416210305.2255579-4-brian.cain@oss.qualcomm.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-Proofpoint-GUID":"xXJz2kdgWz6-Xe1kpnkmZnay_B0PYQ2u","X-Proofpoint-ORIG-GUID":"xXJz2kdgWz6-Xe1kpnkmZnay_B0PYQ2u","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIwMDE2NCBTYWx0ZWRfXwExSDBKBA8+4\n W6fIwu8Np+ik705l/s33bt/5LyOnmwVUZwMfOhlHUknmJndl3biCQgVLao5es6T35ALZn+fjSzK\n s+ZbxOuw+a9tmndZm27C+SLG2kCW7C6Qp0iHx24U+9KK4dN69VuJNt9qg9UnYBn3r1QtWYlqcd2\n 5BpxQzszCMgGy05leuW9nm8tNgb7AdGtMU0Mjberiv21fPZmXQ8kapHarZHPqSwU5bYQmd/+iCX\n GfHqSJUoGcLECYeTzvZA3F0NMxNJsD4ogRiaB4wTK8lLOWvuA0xpVZ7/Esr7z5j1+CJcD4qUxJD\n KUCJOH0wjJoy0/79Z2t+IHY1s3wFWhppY2MjY+o6BHIMxZHE+/+mKQweWVb8yMyzBLMvI79yIIo\n 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3680071,"web_url":"http://patchwork.ozlabs.org/comment/3680071/","msgid":"<1c3088c0-4388-4915-8bb3-c1f11675c093@linaro.org>","list_archive_url":null,"date":"2026-04-21T21:42:39","subject":"Re: [PATCH v5 3/9] hw/hexagon: Add machine configs for sysemu","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 23:02, Brian Cain wrote:\n> From: Brian Cain \n> \n> Some header includes are modified here: these are uniquely required for\n> basic system emulation functionality and had not been required for linux-user.\n> \n> Acked-by: Markus Armbruster \n> Co-authored-by: Mike Lambert \n> Co-authored-by: Sid Manning \n> Signed-off-by: Brian Cain \n> ---\n> MAINTAINERS | 2 +\n> include/hw/hexagon/hexagon.h | 150 +++++++++++++++++++++++\n> hw/hexagon/machine_cfg_v66g_1024.h.inc | 64 ++++++++++\n> hw/hexagon/hexagon_dsp.c | 161 +++++++++++++++++++++++++\n> system/qdev-monitor.c | 2 +-\n> target/hexagon/translate.c | 1 +\n> hw/Kconfig | 1 +\n> hw/hexagon/Kconfig | 4 +\n> hw/hexagon/meson.build | 6 +\n> hw/meson.build | 1 +\n> 10 files changed, 391 insertions(+), 1 deletion(-)\n> create mode 100644 include/hw/hexagon/hexagon.h\n> create mode 100644 hw/hexagon/machine_cfg_v66g_1024.h.inc\n> create mode 100644 hw/hexagon/hexagon_dsp.c\n> create mode 100644 hw/hexagon/Kconfig\n> create mode 100644 hw/hexagon/meson.build\n> \n> diff --git a/MAINTAINERS b/MAINTAINERS\n> index 4055fbe3c21..b9a7c553dfa 100644\n> --- a/MAINTAINERS\n> +++ b/MAINTAINERS\n> @@ -246,6 +246,8 @@ Hexagon TCG CPUs\n> M: Brian Cain \n> S: Supported\n> F: target/hexagon/\n> +F: hw/hexagon/\n> +F: include/hw/hexagon/\n\nIMHO long-term it is better to split architectural code from\nhardware modelling in distinct MAINTAINERS sections (and distinct\nset of reviewers / maintainers / lists).\n\n> X: target/hexagon/idef-parser/\n> X: target/hexagon/gen_idef_parser_funcs.py\n> F: linux-user/hexagon/\n\n\n> +static void hexagon_common_init(MachineState *machine, Rev_t rev,\n> + const struct hexagon_machine_config *m_cfg)\n> +{\n> + MemoryRegion *address_space;\n> + MemoryRegion *sram;\n> + DeviceState *glob_regs_dev;\n> +\n> + memset(&hexagon_binfo, 0, sizeof(hexagon_binfo));\n> + if (machine->kernel_filename) {\n> + hexagon_binfo.ram_size = machine->ram_size;\n> + hexagon_binfo.kernel_filename = machine->kernel_filename;\n> + }\n> +\n> + machine->enable_graphics = 0;\n> +\n> + address_space = get_system_memory();\n> +\n> + sram = g_new(MemoryRegion, 1);\n> + memory_region_init_ram(sram, NULL, \"ddr.ram\",\n\nDDRAM or SRAM?\n\n> + machine->ram_size, &error_fatal);\n> + memory_region_add_subregion(address_space, 0x0, sram);\n> +\n> + glob_regs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);\n> + qdev_prop_set_uint64(glob_regs_dev, \"config-table-addr\", m_cfg->cfgbase);\n> + sysbus_realize_and_unref(SYS_BUS_DEVICE(glob_regs_dev), &error_fatal);\n> +\n> + for (int i = 0; i < machine->smp.cpus; i++) {\n> + HexagonCPU *cpu = HEXAGON_CPU(object_new(machine->cpu_type));\n> + qemu_register_reset(do_cpu_reset, cpu);\n> +\n> + /*\n> + * CPU #0 is the only CPU running at boot, others must be\n> + * explicitly enabled via start instruction.\n> + */\n> + qdev_prop_set_bit(DEVICE(cpu), \"start-powered-off\", (i != 0));\n> + if (i == 0) {\n> + hexagon_init_bootstrap(machine, cpu);\n> + if (!qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal)) {\n> + return;\n> + }\n> + } else if (!qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal)) {\n> + return;\n> + }\n> +\n> + }\n> +}\n> +\n> +static void init_mc(MachineClass *mc)\n> +{\n> + mc->block_default_type = IF_SD;\n\nIs \"By default try to boot on SD Card first\" what you want?\n\n> + mc->default_ram_size = 4 * GiB;\n> + mc->no_parallel = 1;\n> + mc->no_floppy = 1;\n> + mc->no_cdrom = 1;\n> + mc->no_serial = 1;\n> + mc->is_default = false;\n> + mc->max_cpus = 8;\n> +}\n\n\n> diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c\n> index 1ac6d9a8575..72abc9182a9 100644\n> --- a/system/qdev-monitor.c\n> +++ b/system/qdev-monitor.c\n> @@ -69,7 +69,7 @@ typedef struct QDevAlias\n> QEMU_ARCH_SPARC | \\\n> QEMU_ARCH_XTENSA)\n> #define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)\n> -#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)\n> +#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K | QEMU_ARCH_HEXAGON)\n> \n> /* Please keep this table sorted by typename. */\n> static const QDevAlias qdev_alias_table[] = {\n> diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\n> index ae980c087f0..15258a203b3 100644\n> --- a/target/hexagon/translate.c\n> +++ b/target/hexagon/translate.c\n> @@ -32,6 +32,7 @@\n> #include \"translate.h\"\n> #include \"genptr.h\"\n> #include \"printinsn.h\"\n> +#include \"exec/target_page.h\"\n\nRebase left-over?\n\n> \n> #define HELPER_H \"helper.h\"\n> #include \"exec/helper-info.c.inc\"\n\n\n> diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build\n> new file mode 100644\n> index 00000000000..f528d2bc4ab\n> --- /dev/null\n> +++ b/hw/hexagon/meson.build\n> @@ -0,0 +1,6 @@\n> +hexagon_ss = ss.source_set()\n> +hexagon_ss.add(files('hexagon_tlb.c'))\n> +hexagon_ss.add(files('hexagon_globalreg.c'))\n> +hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c'))\n> +\n> +hw_arch += {'hexagon': hexagon_ss}\n\nBetter would be:\n\n hw_common_arch += {'hexagon': hexagon_common_ss}\n\nPierrick can help here!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=pwyhb1hI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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