[{"id":3678417,"web_url":"http://patchwork.ozlabs.org/comment/3678417/","msgid":"<73a6d4c3-9108-4172-b1b6-11ee857909fc@linaro.org>","list_archive_url":null,"date":"2026-04-16T22:49:20","subject":"Re: [PATCH v4 2/2] target/mips: Use probe_access_full() in Atomic\n Load/Store helpers","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/17/26 01:06, Philippe Mathieu-Daudé wrote:\n> Let the probe_access() API check the address alignment.\n\nThe probe_access will not check the alignment.\nThe use of the memory access before the probe checks the alignment.\n\n> \n> Move env->CP0_LLAddr and env->lladdr assignments so we\n> don't update them when an alignment fault occurs.\n> \n> Since we have a handy MemOpIdx, replace the legacy\n> cpu_ld*_mmuidx_ra() calls by cpu_ld*_mmu() equivalent.\n> \n> Suggested-by: Richard Henderson \n> Signed-off-by: Philippe Mathieu-Daudé \n> ---\n> target/mips/tcg/ldst_helper.c | 21 +++++++++++++++------\n> 1 file changed, 15 insertions(+), 6 deletions(-)\n> \n> diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c\n> index b725c6d0333..4ebf72d610e 100644\n> --- a/target/mips/tcg/ldst_helper.c\n> +++ b/target/mips/tcg/ldst_helper.c\n> @@ -28,23 +28,32 @@\n> #include \"internal.h\"\n> \n> #ifndef CONFIG_USER_ONLY\n> +#include \"accel/tcg/probe.h\"\n> +#include \"exec/tlb-flags.h\"\n> \n> #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \\\n> target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, \\\n> uint32_t memop_idx) \\\n> { \\\n> - MemOpIdx oi = memop_idx; \\\n> - unsigned mem_idx = get_mmuidx(oi); \\\n> - if (arg & almask) { \\\n> + MemOpIdx oi = memop_idx; \\\n> + unsigned mem_idx = get_mmuidx(oi); \\\n> + unsigned size = memop_size(get_memop(oi)); \\\n> + uintptr_t ra = GETPC(); \\\n> + CPUTLBEntryFull *full; \\\n> + void *host_unused; \\\n> + int flags; \\\n> + \\\n> + env->llval = do_cast cpu_##insn##_mmu(env, arg, oi, ra); \\\n\nThis performs the access, filling the tlb in the process.\nIf the tlb cannot be filled, access is not permitted an an exception is raised.\n\n> + flags = probe_access_full(env, arg, size, MMU_DATA_LOAD, mem_idx, \\\n> + true, &host_unused, &full, ra); \\\n\nWhich means this probe for the tlb entry *must* succeed, because we can't reach here \nunless it was confirmed present by the access above.\n\n> + if (unlikely(flags & TLB_INVALID_MASK)) { \n\nWhich means this must be\n\n assert(!(flags & TLB_INVALID_MASK));\n \\\n> if (!(env->hflags & MIPS_HFLAG_DM)) { \\\n> env->CP0_BadVAddr = arg; \\\n> } \\\n> do_raise_exception(env, EXCP_AdEL, GETPC()); \\\n> } \n\n... and the rest of the IF is dead code.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HeqEODwL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxY9v2Wtjz1yD3\n\tfor ; Fri, 17 Apr 2026 08:49:53 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDVWd-0002ws-Cr; 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