[{"id":3678363,"web_url":"http://patchwork.ozlabs.org/comment/3678363/","msgid":"","list_archive_url":null,"date":"2026-04-16T20:03:12","subject":"Re: [PATCH pciutils] ls-ecaps: Decode DPC RP PIO registers","submitter":{"id":8506,"url":"http://patchwork.ozlabs.org/api/people/8506/","name":"Martin Mareš","email":"mj@ucw.cz"},"content":"Hello!\n\n> +#define PCI_DPC_RP_PIO_EXCEPTION\t0x1C\t/* DPC RP PIO Exception */\n\nWe use lower-case hex digits.\n\n> + if ((cap & PCI_DPC_CAP_RP_EXT) && config_fetch(d, where + PCI_DPC_CAP + 8, 24 + 4 * log_size)) {\n\nPlease follow the indentation style of the rest of the file.\n\n> + printf(\"\\t\\tRP PIO:\\n\");\n> +\n> + l = get_conf_long(d, where + PCI_DPC_RP_PIO_STATUS);\n> + printf(\"\\t\\t\\tSta: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> +\n> + l = get_conf_long(d, where + PCI_DPC_RP_PIO_MASK);\n> + printf(\"\\t\\t\\tMsk: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> +\n> + l = get_conf_long(d, where + PCI_DPC_RP_PIO_SEVERITY);\n> + printf(\"\\t\\t\\tSev: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> +\n> + l = get_conf_long(d, where + PCI_DPC_RP_PIO_SYSERROR);\n> + printf(\"\\t\\t\\tErr: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> +\n> + l = get_conf_long(d, where + PCI_DPC_RP_PIO_EXCEPTION);\n> + printf(\"\\t\\t\\tExc: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> +\n> + l0 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG);\n> + l1 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 4);\n> + l2 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 8);\n> + l3 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 12);\n\nShouldn't you check that the log is long enough before accessing the\nfirst 4 entries?\n\n\t\t\t\tMartin","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ucw.cz header.i=@ucw.cz header.a=rsa-sha256\n header.s=gen1 header.b=Kc0QOxXu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n 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in-reply-to:in-reply-to:references:references;\n\tbh=D7kEVMC1ak29EXqM+Wu5Pvij8q2P6GWJvi8FgJTpEDY=;\n\tb=Kc0QOxXuL2BFQLFsO7GjaUJhxmGfQHH8B19zYH0Q2vHF1p5QeT4Qt8nRVhV0ngDIaHbdK/\n\tiz1yhEQweot0ol30xk0V4LPevWZzLwp5O82Hd0uJ/okDjrtanClDdR5OQmPjmNvmWsr65J\n\t8ezZxWMWOGQFCF4eXu1tDP3Wi+XPhBM=","Date":"Thu, 16 Apr 2026 22:03:12 +0200","From":"Martin =?utf-8?b?TWFyZcWh?= ","To":"Mattias Nissler ","Cc":"linux-pci@vger.kernel.org","Subject":"Re: [PATCH pciutils] ls-ecaps: Decode DPC RP PIO registers","Message-ID":"","References":"<20260416125706.3875359-1-mnissler@meta.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260416125706.3875359-1-mnissler@meta.com>"}},{"id":3678518,"web_url":"http://patchwork.ozlabs.org/comment/3678518/","msgid":"","list_archive_url":null,"date":"2026-04-17T06:49:09","subject":"Re: [PATCH pciutils] ls-ecaps: Decode DPC RP PIO registers","submitter":{"id":93169,"url":"http://patchwork.ozlabs.org/api/people/93169/","name":"Mattias Nissler","email":"mnissler@meta.com"},"content":"On Thu, Apr 16, 2026 at 10:03 PM Martin Mareš wrote:\n>\n> >\n> Hello!\n>\n> > +#define PCI_DPC_RP_PIO_EXCEPTION 0x1C /* DPC RP PIO Exception */\n>\n> We use lower-case hex digits.\n\nAck, will update.\n\n>\n> > + if ((cap & PCI_DPC_CAP_RP_EXT) && config_fetch(d, where + PCI_DPC_CAP + 8, 24 + 4 * log_size)) {\n>\n> Please follow the indentation style of the rest of the file.\n\nAck, adjusting.\n\n>\n> > + printf(\"\\t\\tRP PIO:\\n\");\n> > +\n> > + l = get_conf_long(d, where + PCI_DPC_RP_PIO_STATUS);\n> > + printf(\"\\t\\t\\tSta: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> > + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> > +\n> > + l = get_conf_long(d, where + PCI_DPC_RP_PIO_MASK);\n> > + printf(\"\\t\\t\\tMsk: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> > + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> > +\n> > + l = get_conf_long(d, where + PCI_DPC_RP_PIO_SEVERITY);\n> > + printf(\"\\t\\t\\tSev: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> > + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> > +\n> > + l = get_conf_long(d, where + PCI_DPC_RP_PIO_SYSERROR);\n> > + printf(\"\\t\\t\\tErr: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> > + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> > +\n> > + l = get_conf_long(d, where + PCI_DPC_RP_PIO_EXCEPTION);\n> > + printf(\"\\t\\t\\tExc: CfgUR%c CfgCA%c CfgCTO%c IOUR%c IOCA%c IOCTO%c MemUR%c MemCA%c MemCTO%c\\n\",\n> > + FLAG(l, PCI_DPC_RP_PIO_CFG_UR), FLAG(l, PCI_DPC_RP_PIO_CFG_CA), FLAG(l, PCI_DPC_RP_PIO_CFG_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_IO_UR), FLAG(l, PCI_DPC_RP_PIO_IO_CA), FLAG(l, PCI_DPC_RP_PIO_IO_CTO),\n> > + FLAG(l, PCI_DPC_RP_PIO_MEM_UR), FLAG(l, PCI_DPC_RP_PIO_MEM_CA), FLAG(l, PCI_DPC_RP_PIO_MEM_CTO));\n> > +\n> > + l0 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG);\n> > + l1 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 4);\n> > + l2 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 8);\n> > + l3 = get_conf_long(d, where + PCI_DPC_RP_PIO_HEADER_LOG + 12);\n>\n> Shouldn't you check that the log is long enough before accessing the\n> first 4 entries?\n\nPer the spec, the 4DW Header Log register is always present, and there\nis language requiring the log size field to be >= 4.\n\nAlso, my understanding is that this is intentionally analogous to the\nAER Header Log register, so I took the same approach as used for that.\n\n>\n> Martin","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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definitions=2026-04-16_04,2026-04-16_03,2025-10-01_01"}},{"id":3678651,"web_url":"http://patchwork.ozlabs.org/comment/3678651/","msgid":"","list_archive_url":null,"date":"2026-04-17T10:19:58","subject":"Re: [PATCH pciutils] ls-ecaps: Decode DPC RP PIO registers","submitter":{"id":8506,"url":"http://patchwork.ozlabs.org/api/people/8506/","name":"Martin Mareš","email":"mj@ucw.cz"},"content":"Hi!\n\n> Ack, will update.\n\nIt's better, thanks!\n\n> Per the spec, the 4DW Header Log register is always present, and there\n> is language requiring the log size field to be >= 4.\n\nI know, but I've seen too many devices violating specs...\n\nGenerally, the pciutils try to cope with whatever incorrect data the\nhardware reports. It particular, they should not crash nor get caught\nin an infinite loop.\n\nIf the log size field were < 4, your code would call get_conf_long()\non a part of the configuration space that was not read by a previous\nconfig_fetch(), which would trigger an internal error.\n\nA simple fix is to condition printing the HeaderLog on log_size >= 4.\n\n> Also, my understanding is that this is intentionally analogous to the\n> AER Header Log register, so I took the same approach as used for that.\n\nThat's fine, but in case of the AER Header Log, the config_fetch()\nhas a fixed size, which always covers the log entries.\n\n\t\t\t\tHave a nice day","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ucw.cz header.i=@ucw.cz header.a=rsa-sha256\n header.s=gen1 header.b=OPlcKDu/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=rsa-sha256; c=relaxed/relaxed; d=ucw.cz; s=gen1;\n\tt=1776421198;\n\th=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n\t to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n\t content-transfer-encoding:content-transfer-encoding:\n\t in-reply-to:in-reply-to:references:references;\n\tbh=DdrLUT9la43oQwWwNxiSXX7ddlzx6kuA7+yNCZJ0NWE=;\n\tb=OPlcKDu/i+qylEAnllYPIT50CpEF68qs6W+0ZClm7UQnuvCxgLiHI8SandZqt+5NV3DN4G\n\ts5AAhJa80AyCdFK+tr4YhBifFapsFiWTXQgTnp/wEuY7InYfVQTyGseBR2ZWAS8QJ8lYIq\n\tAVxcBj8nbtCsRoeFUPoE3PjzJLKdPts=","Date":"Fri, 17 Apr 2026 12:19:58 +0200","From":"Martin =?utf-8?b?TWFyZcWh?= ","To":"Mattias Nissler ","Cc":"linux-pci@vger.kernel.org","Subject":"Re: [PATCH pciutils] ls-ecaps: Decode DPC RP PIO registers","Message-ID":"","References":"<20260416125706.3875359-1-mnissler@meta.com>\n \n ","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"\n "}},{"id":3678653,"web_url":"http://patchwork.ozlabs.org/comment/3678653/","msgid":"","list_archive_url":null,"date":"2026-04-17T10:35:30","subject":"Re: [PATCH pciutils] ls-ecaps: Decode DPC RP PIO registers","submitter":{"id":93169,"url":"http://patchwork.ozlabs.org/api/people/93169/","name":"Mattias Nissler","email":"mnissler@meta.com"},"content":"On Fri, Apr 17, 2026 at 12:20 PM Martin Mareš wrote:\n>\n> >\n> Hi!\n>\n> > Ack, will update.\n>\n> It's better, thanks!\n>\n> > Per the spec, the 4DW Header Log register is always present, and there\n> > is language requiring the log size field to be >= 4.\n>\n> I know, but I've seen too many devices violating specs...\n>\n> Generally, the pciutils try to cope with whatever incorrect data the\n> hardware reports. It particular, they should not crash nor get caught\n> in an infinite loop.\n>\n> If the log size field were < 4, your code would call get_conf_long()\n> on a part of the configuration space that was not read by a previous\n> config_fetch(), which would trigger an internal error.\n>\n> A simple fix is to condition printing the HeaderLog on log_size >= 4.\n\nAh, you're right, I had overlooked the config_fetch angle of this. Let\nme add the check as suggested.\n\n>\n> > Also, my understanding is that this is intentionally analogous to the\n> > AER Header Log register, so I took the same approach as used for that.\n>\n> That's fine, but in case of the AER Header Log, the config_fetch()\n> has a fixed size, which always covers the log entries.\n>\n> Have a nice day\n> --\n> Martin `MJ' Mareš https://urldefense.com/v3/__http://mj.ucw.cz/__;!!Bt8RZUm9aw!-k2ThkLRdBtx6B1hSdcfTt_X77CluV8P_POzwnd1bnjYf_8tS900yCUARV58jcCfD7LS3XA$\n> United Computer Wizards, Prague, Czech Republic, Europe, Earth, Universe","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=meta.com header.i=@meta.com header.a=rsa-sha256\n header.s=s2048-2025-q2 header.b=tNnDgtJJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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