[{"id":3679314,"web_url":"http://patchwork.ozlabs.org/comment/3679314/","msgid":"<03c15a36-0502-3344-e941-6b239d04ce22@loongson.cn>","list_archive_url":null,"date":"2026-04-20T09:10:23","subject":"Re: [PATCH v3] target/loongarch: Add support for dbar hint variants","submitter":{"id":78914,"url":"http://patchwork.ozlabs.org/api/people/78914/","name":"Bibo Mao","email":"maobibo@loongson.cn"},"content":"On 2026/4/16 下午7:47, Song Gao wrote:\n> LoongArch architecture (since LA664) introduces fine-grained dbar\n> hints that allow controlling which memory accesses are ordered by\n> the barrier. Previously, all dbar instructions were treated as a\n> full barrier (TCG_MO_ALL | TCG_BAR_SC).\n> \n> This patch adds support for decoding dbar hints and emitting the\n> appropriate TCG memory barrier flags. For CPUs that do not advertise\n> the DBAR_HINTS feature (cpucfg3.DBAR_HINTS = 0), all dbar hints\n> fall back to a full barrier, preserving compatibility.\n> \n> The hint encoding follows the LoongArch v1.10 specification:\n> The hint is a 5-bit field (bits 4-0). Bit4 is reserved and currently\n> ignored/discarded. Only bits 3-0 are used for ordering control.\n> * Bit3: barrier for previous read (0: true, 1: false)\n> * Bit2: barrier for previous write (0: true, 1: false)\n> * Bit1: barrier for succeeding read (0: true, 1: false)\n> * Bit0: barrier for succeeding write (0: true, 1: false)\n> \n> The mapping to TCG memory order flags is as follows:\n> TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_LD_ST;\n> TCG_BAR_SC |TCG_MO_ST_LD | TCG_MO_ST_ST;\n> TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_ST_LD;\n> TCG_BAR_SC |TCG_MO_ST_ST | TCG_MO_LD_ST;\n> \n> Special hint handling:\n> - hint 0x700: LL/SC loop barrier, treated as a full barrier as recommended.\n> - hint 0xf and 0x1f: reserved/no-op, treated as no operation\n> \n> Signed-off-by: Song Gao \n> ---\n> target/loongarch/cpu.c | 4 ++\n> .../tcg/insn_trans/trans_memory.c.inc | 63 ++++++++++++++++++-\n> target/loongarch/tcg/translate.c | 1 +\n> target/loongarch/translate.h | 3 +\n> 4 files changed, 69 insertions(+), 2 deletions(-)\n> \n> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\n> index e22568c84a..d8d106b07e 100644\n> --- a/target/loongarch/cpu.c\n> +++ b/target/loongarch/cpu.c\n> @@ -455,6 +455,10 @@ static void loongarch_max_initfn(Object *obj)\n> data = FIELD_DP32(data, CPUCFG2, LLACQ_SCREL, 1);\n> data = FIELD_DP32(data, CPUCFG2, SCQ, 1);\n> cpu->env.cpucfg[2] = data;\n> +\n> + data = cpu->env.cpucfg[3];\n> + data = FIELD_DP32(data, CPUCFG3, DBAR_HINTS, 1);\n> + cpu->env.cpucfg[3] = data;\n> }\n> }\n> \n> diff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n> index e287d46363..dcecf02e54 100644\n> --- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n> +++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n> @@ -137,11 +137,70 @@ static bool trans_preldx(DisasContext *ctx, arg_preldx * a)\n> return true;\n> }\n> \n> +/*\n> + * Decode dbar hint and emit appropriate TCG memory barrier.\n> + *\n> + * The hint is a 5-bit field (0-31) encoded in the instruction.\n> + * For hint 0x700 (special LL/SC loop barrier), treat as full barrier.\n> + *\n> + * See LoongArch Reference Manual v1.10, Section 4.2.2 for details.\n> + */\n> static bool trans_dbar(DisasContext *ctx, arg_dbar * a)\n> {\n> - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);\n> + int hint = a->imm;\n> + TCGBar bar_flags = 0;\n> +\n> + /* Reserved/no-op hints: 0xf and 0x1f */\n> + if (hint == 0xf || hint == 0x1f) {\n> + return true;\n> + }\n> +\n> + /* If the CPU does not support fine-grained hints,or for the special LL/SC\n> + * loop barrier (0x700), emit a full barrier.\n> + */\n> + if (!avail_DBAR_HINT(ctx) || hint == 0x700) {\n> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n> + return true;\n> + }\n> +\n> + /*\n> + * Fine-grained hint decoding:\n> + * The hint is a 5-bit field (bits 4-0). Bit4 is reserved and currently\n> + * ignored/discarded. Only bits 3-0 are used for ordering control.\n> + * Bit3: barrier for previous read (0: true, 1: false)\n> + * Bit2: barrier for previous write (0: true, 1: false)\n> + * Bit1: barrier for succeeding read (0: true, 1: false)\n> + * Bit0: barrier for succeeding write (0: true, 1: false)\n> + *\n> + * For each combination, we set the corresponding TCG_MO_* flag if both\n> + * sides of the barrier require ordering.\n> + */\n> +\n> + bool prev_rd = !(hint & 0x08); /* bit3 */\n> + bool prev_wr = !(hint & 0x04); /* bit2 */\n> + bool succ_rd = !(hint & 0x02); /* bit1 */\n> + bool succ_wr = !(hint & 0x01); /* bit0 */\n> +\n> + if (prev_rd) {\n> + bar_flags |= TCG_MO_LD_LD | TCG_MO_LD_ST;\n> + }\n> + if (prev_wr) {\n> + bar_flags |= TCG_MO_ST_LD | TCG_MO_ST_ST;\n> + }\n> + if (succ_rd) {\n> + bar_flags |= TCG_MO_LD_LD | TCG_MO_ST_LD;\n> + }\n> + if (succ_wr) {\n> + bar_flags |= TCG_MO_ST_ST | TCG_MO_LD_ST;\n> + }\n> +\n> + if (bar_flags == 0) {\n> + bar_flags = TCG_MO_ALL;\n> + }\n> +\n> + tcg_gen_mb(bar_flags | TCG_BAR_SC);\n> return true;\n> -}\n> + }\n> \n> static bool trans_ibar(DisasContext *ctx, arg_ibar *a)\n> {\n> diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c\n> index b9ed13d19c..49280b1dd3 100644\n> --- a/target/loongarch/tcg/translate.c\n> +++ b/target/loongarch/tcg/translate.c\n> @@ -149,6 +149,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n> \n> ctx->cpucfg1 = env->cpucfg[1];\n> ctx->cpucfg2 = env->cpucfg[2];\n> + ctx->cpucfg3 = env->cpucfg[3];\n> }\n> \n> static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)\n> diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\n> index ba1c89e57b..8aa8325dc6 100644\n> --- a/target/loongarch/translate.h\n> +++ b/target/loongarch/translate.h\n> @@ -43,6 +43,8 @@\n> #define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_SCREL))\n> #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))\n> \n> +#define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, DBAR_HINTS))\n> +\n> /*\n> * If an operation is being performed on less than TARGET_LONG_BITS,\n> * it may require the inputs to be sign- or zero-extended; which will\n> @@ -66,6 +68,7 @@ typedef struct DisasContext {\n> bool va32; /* 32-bit virtual address */\n> uint32_t cpucfg1;\n> uint32_t cpucfg2;\n> + uint32_t cpucfg3;\n> } DisasContext;\n> \n> void generate_exception(DisasContext *ctx, int excp);\n> \nReviewed-by: Bibo Mao ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzftx3rXPz1yGs\n\tfor ; Mon, 20 Apr 2026 19:14:16 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wEkhA-0001Gq-Ta; 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