[{"id":3678372,"web_url":"http://patchwork.ozlabs.org/comment/3678372/","msgid":"<20260416203905.GA29913@bhelgaas>","list_archive_url":null,"date":"2026-04-16T20:39:05","subject":"Re: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Thu, Apr 16, 2026 at 07:14:12PM +0800, Sherry Sun wrote:\n> Introduce generic helper functions to parse Root Port device tree nodes\n> and extract common properties like reset GPIOs. This allows multiple\n> PCI host controller drivers to share the same parsing logic.\n> \n> Define struct pci_host_port to hold common Root Port properties\n> (currently only reset GPIO descriptor) and add\n> pci_host_common_parse_ports() to parse Root Port nodes from device tree.\n\nAre the Root Port and the RC the only possible places for 'reset' GPIO\ndescriptions in DT? I think PERST# routing is outside the PCIe spec,\nso it seems like a system could provide a PERST# GPIO routed to any\nSwitch Upstream Port or Endpoint (I assume a PERST# connected to a\nswitch would apply to both the upstream port and the downstream\nports).","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=NIC+uZOP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-52653-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"NIC+uZOP\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxVH76HmGz1yD3\n\tfor ; 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a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776371947; c=relaxed/simple;\n\tbh=RhBffrmsMOEQ9U00Vb6PjZXRgwm+dO9ZID94mEWA0Ak=;\n\th=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type:\n\t Content-Disposition:In-Reply-To;\n b=Kp7leOS5DE6VbFlZeXWD+3UXRMb8AfIpjaSWvrOzlfFDRtA2MjFBhZOIu00komA6UjFqdJRf7fP76yXOX/YQfRJDTghvRMKat+A1blXHsm40gQ/jh/HZBJ4qmU43l+acBEz5pR5xVP9GHsAh4+lkP0G/DzF3uWeQsBYPaPD7/yw=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=NIC+uZOP; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1776371946;\n\tbh=RhBffrmsMOEQ9U00Vb6PjZXRgwm+dO9ZID94mEWA0Ak=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:From;\n\tb=NIC+uZOPOTFu7mybYkK3oTnc3bdL2r8txodTtcrLDkhApF+K+rfsBdgJQ6aSWThkY\n\t JqpOvSaL0mArNGzN2M0iMSmFbee7mQNnEvqfAqWTLv6U1KEfdTbwejpFRsj+fVtIsb\n\t wSB1W7m+2Y7VxZfP8etFbgvKsjrTIkLkEtJ5SYXL4uJdRKyzpjQ/ujP14rk/WfLYuM\n\t fBLieuO+kfgLbJeeCbzU2S7ImUhAdGLeQU5oXRt9tS31b98FJutEdKNSmOLoQdXJtR\n\t 5Yq1GPtrt6yU21YRfIkHj1q/eLrGVHyqMdgbL0cy86aAHatdAKBahoPgjxliq8Dlw2\n\t my5ITqYYZj0BQ==","Date":"Thu, 16 Apr 2026 15:39:05 -0500","From":"Bjorn Helgaas ","To":"Sherry Sun ","Cc":"robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,\n\tFrank.Li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de,\n\tfestevam@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org,\n\tmani@kernel.org, bhelgaas@google.com, hongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de, imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","Message-ID":"<20260416203905.GA29913@bhelgaas>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260416111422.183860-3-sherry.sun@nxp.com>"}},{"id":3678465,"web_url":"http://patchwork.ozlabs.org/comment/3678465/","msgid":"","list_archive_url":null,"date":"2026-04-17T03:17:16","subject":"RE: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"content":"> On Thu, Apr 16, 2026 at 07:14:12PM +0800, Sherry Sun wrote:\n> > Introduce generic helper functions to parse Root Port device tree\n> > nodes and extract common properties like reset GPIOs. This allows\n> > multiple PCI host controller drivers to share the same parsing logic.\n> >\n> > Define struct pci_host_port to hold common Root Port properties\n> > (currently only reset GPIO descriptor) and add\n> > pci_host_common_parse_ports() to parse Root Port nodes from device\n> tree.\n> \n> Are the Root Port and the RC the only possible places for 'reset' GPIO\n> descriptions in DT? I think PERST# routing is outside the PCIe spec, so it\n> seems like a system could provide a PERST# GPIO routed to any Switch\n> Upstream Port or Endpoint (I assume a PERST# connected to a switch would\n> apply to both the upstream port and the downstream ports).\n\nHi Bjorn,\n\nThanks for the feedback. You're right that PERST# routing could theoretically be\nconnected to any device in the hierarchy. However, for this patch series, I've focused\non the most common use case in practice: use Root Port level PERST# instead of the\nlegacy Root Complex level PERST#.\n\nRoot Port level PERST# - This is the primary target, where each Root Port has individual\ncontrol over devices connected to it.\nRC level PERST# - Legacy binding support, where a single GPIO controls all ports.\n\nWe can extend this framework later if real hardware emerges that needs Switch or\nEP-level PERST# control. I can add a comment documenting this limitation if needed.\n\nBTW, Mani and Rob had some great discussions in dt-schema about PERST# and WAKE#\nsideband signals settings.\nYou can check here:\nhttps://github.com/devicetree-org/dt-schema/issues/168\nhttps://github.com/devicetree-org/dt-schema/pull/126\nhttps://github.com/devicetree-org/dt-schema/pull/170\n\nBest Regards\nSherry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=neKor8hf;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52680-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com\n header.b=\"neKor8hf\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.159.27","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=nxp.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=nxp.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxg7v2YTrz1yD3\n\tfor ; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"quoted-printable","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 31cdc49b-118a-4f80-b97a-08de9c2fd3e4","X-MS-Exchange-CrossTenant-originalarrivaltime":"17 Apr 2026 03:17:16.5279\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n m8kzFib327Xh6xMpSpeD5lpgCFemiEBMr5Rg/E/uSri75ahCK74H6/IIoEsBbrqD5gI6zdkpLpkdE9HRtY83nQ==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DBBPR04MB7787"}},{"id":3678870,"web_url":"http://patchwork.ozlabs.org/comment/3678870/","msgid":"<20260417195533.GA92707@bhelgaas>","list_archive_url":null,"date":"2026-04-17T19:55:33","subject":"Re: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Fri, Apr 17, 2026 at 03:17:16AM +0000, Sherry Sun wrote:\n> > On Thu, Apr 16, 2026 at 07:14:12PM +0800, Sherry Sun wrote:\n> > > Introduce generic helper functions to parse Root Port device\n> > > tree nodes and extract common properties like reset GPIOs. This\n> > > allows multiple PCI host controller drivers to share the same\n> > > parsing logic.\n> > >\n> > > Define struct pci_host_port to hold common Root Port properties\n> > > (currently only reset GPIO descriptor) and add\n> > > pci_host_common_parse_ports() to parse Root Port nodes from\n> > > device tree.\n> > \n> > Are the Root Port and the RC the only possible places for 'reset'\n> > GPIO descriptions in DT? I think PERST# routing is outside the\n> > PCIe spec, so it seems like a system could provide a PERST# GPIO\n> > routed to any Switch Upstream Port or Endpoint (I assume a PERST#\n> > connected to a switch would apply to both the upstream port and\n> > the downstream ports).\n> \n> Thanks for the feedback. You're right that PERST# routing could\n> theoretically be connected to any device in the hierarchy. However,\n> for this patch series, I've focused on the most common use case in\n> practice: use Root Port level PERST# instead of the legacy Root\n> Complex level PERST#.\n> \n> Root Port level PERST# - This is the primary target, where each Root\n> Port has individual control over devices connected to it. RC level\n> PERST# - Legacy binding support, where a single GPIO controls all\n> ports.\n> \n> We can extend this framework later if real hardware emerges that\n> needs Switch or EP-level PERST# control. I can add a comment\n> documenting this limitation if needed.\n> \n> BTW, Mani and Rob had some great discussions in dt-schema about\n> PERST# and WAKE# sideband signals settings.\n\n> You can check here:\n> https://github.com/devicetree-org/dt-schema/issues/168\n> https://github.com/devicetree-org/dt-schema/pull/126\n> https://github.com/devicetree-org/dt-schema/pull/170\n\nThe upshot of all those conversations is that WAKE# and PERST# can be\nrouted to arbitrary devices independent of the PCI topology.\n\nI think extending host-generic to look for 'reset' in Root Port nodes\nis the right thing. My concern is more about where we store it. This\npatch saves it in a new \"pci_host_port\" struct, but someday we'll want\na place to save the PERST# GPIOs for several slots behind a switch.\nThen we'll have two different ways to save the same information.\n\nWAKE# signals might be more pertinent -- we definitely need to support\nmultiple WAKE# signals below a single Root Port, and it seems like\nPERST# and WAKE# GPIOs should be saved the same place.\n\nI'm wondering if both should go in the pci_dev itself. I guess the\nimplication is that a pci_dev->reset GPIO would describe a PERST#\nconnected to the device *below* the pci_dev, at least for Downstream\nPorts.\n\nI don't know about WAKE# signals. When it's in a connector, there's\nprobably only a single possible WAKE# per Downstream Port. But is it\npossible have multiple WAKE# signals from a multi-function device\nthat's on the motherboard? Saving the WAKE# GPIO in the Downstream\nPort wouldn't accommodate that case.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=oeyODZQ7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52728-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"oeyODZQ7\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy5HT61m3z1yHp\n\tfor ; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"\n "}},{"id":3679199,"web_url":"http://patchwork.ozlabs.org/comment/3679199/","msgid":"","list_archive_url":null,"date":"2026-04-20T02:59:04","subject":"RE: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"content":"> On Fri, Apr 17, 2026 at 03:17:16AM +0000, Sherry Sun wrote:\n> > > On Thu, Apr 16, 2026 at 07:14:12PM +0800, Sherry Sun wrote:\n> > > > Introduce generic helper functions to parse Root Port device tree\n> > > > nodes and extract common properties like reset GPIOs. This allows\n> > > > multiple PCI host controller drivers to share the same parsing\n> > > > logic.\n> > > >\n> > > > Define struct pci_host_port to hold common Root Port properties\n> > > > (currently only reset GPIO descriptor) and add\n> > > > pci_host_common_parse_ports() to parse Root Port nodes from device\n> > > > tree.\n> > >\n> > > Are the Root Port and the RC the only possible places for 'reset'\n> > > GPIO descriptions in DT? I think PERST# routing is outside the PCIe\n> > > spec, so it seems like a system could provide a PERST# GPIO routed\n> > > to any Switch Upstream Port or Endpoint (I assume a PERST# connected\n> > > to a switch would apply to both the upstream port and the downstream\n> > > ports).\n> >\n> > Thanks for the feedback. You're right that PERST# routing could\n> > theoretically be connected to any device in the hierarchy. However,\n> > for this patch series, I've focused on the most common use case in\n> > practice: use Root Port level PERST# instead of the legacy Root\n> > Complex level PERST#.\n> >\n> > Root Port level PERST# - This is the primary target, where each Root\n> > Port has individual control over devices connected to it. RC level\n> > PERST# - Legacy binding support, where a single GPIO controls all\n> > ports.\n> >\n> > We can extend this framework later if real hardware emerges that needs\n> > Switch or EP-level PERST# control. I can add a comment documenting\n> > this limitation if needed.\n> >\n> > BTW, Mani and Rob had some great discussions in dt-schema about PERST#\n> > and WAKE# sideband signals settings.\n> \n> > You can check here:\n> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith\n> > ub.com%2Fdevicetree-org%2Fdt-\n> schema%2Fissues%2F168&data=05%7C02%7Csher\n> >\n> ry.sun%40nxp.com%7Cd68515fdc0f842ac82d708de9cbb4b2e%7C686ea1d3bc\n> 2b4c6f\n> >\n> a92cd99c5c301635%7C0%7C0%7C639120525411363026%7CUnknown%7CTW\n> FpbGZsb3d8\n> >\n> eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIj\n> oiTW\n> >\n> FpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=ISzWCMSwqYBdw5w%2\n> BDB5ERK51Dr\n> > Tf2jzGtGh3wKNCMZ8%3D&reserved=0\n> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith\n> > ub.com%2Fdevicetree-org%2Fdt-\n> schema%2Fpull%2F126&data=05%7C02%7Csherry\n> > .sun%40nxp.com%7Cd68515fdc0f842ac82d708de9cbb4b2e%7C686ea1d3bc\n> 2b4c6fa9\n> >\n> 2cd99c5c301635%7C0%7C0%7C639120525411380537%7CUnknown%7CTWFp\n> bGZsb3d8ey\n> >\n> JFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiT\n> WFp\n> >\n> bCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=5cohkQIgl0CDlrOmD0dDIbj\n> Q3%2BVg\n> > VOhiOMDRQD1iwLM%3D&reserved=0\n> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith\n> > ub.com%2Fdevicetree-org%2Fdt-\n> schema%2Fpull%2F170&data=05%7C02%7Csherry\n> > .sun%40nxp.com%7Cd68515fdc0f842ac82d708de9cbb4b2e%7C686ea1d3bc\n> 2b4c6fa9\n> >\n> 2cd99c5c301635%7C0%7C0%7C639120525411391138%7CUnknown%7CTWFp\n> bGZsb3d8ey\n> >\n> JFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiT\n> WFp\n> >\n> bCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=WtjyGdvt4s84HynGc3%2F0\n> K3UfkZii\n> > naNAW1ypEd%2B11RY%3D&reserved=0\n> \n> The upshot of all those conversations is that WAKE# and PERST# can be\n> routed to arbitrary devices independent of the PCI topology.\n> \n> I think extending host-generic to look for 'reset' in Root Port nodes is the right\n> thing. My concern is more about where we store it. This patch saves it in a\n> new \"pci_host_port\" struct, but someday we'll want a place to save the\n> PERST# GPIOs for several slots behind a switch.\n> Then we'll have two different ways to save the same information.\n> \n> WAKE# signals might be more pertinent -- we definitely need to support\n> multiple WAKE# signals below a single Root Port, and it seems like PERST#\n> and WAKE# GPIOs should be saved the same place.\n> \n> I'm wondering if both should go in the pci_dev itself. I guess the implication\n> is that a pci_dev->reset GPIO would describe a PERST# connected to the\n> device *below* the pci_dev, at least for Downstream Ports.\n\nHi Bjorn,\nOk, understand your concern, currently I've defined the struct pci_host_port to\nstore the common Root Port properties and added the list of 'ports' to struct\npci_host_bridge.\nI will let @mani to comment and see if this is the appropriate place to store\nthese info, or if we should store them in struct pci_dev. Mani, can you please help?\n\nBut for now, the motivation for this patch is that many PCI host controller drivers\ncurrently share the same requirement: extracting common Root Port properties like\nreset GPIOs (at least currently in many drivers, perst is placed in the root port). We\nintroduce generic helper functions to parse the Root Port t device tree nodes and extract\nthese properties so that multiple PCI drivers can share the same parsing logic. I'm not\nsure if we should take a step forward here anyway?\n\nBest Regards\nSherry\n> \n> I don't know about WAKE# signals. When it's in a connector, there's probably\n> only a single possible WAKE# per Downstream Port. But is it possible have\n> multiple WAKE# signals from a multi-function device that's on the\n> motherboard? Saving the WAKE# GPIO in the Downstream Port wouldn't\n> accommodate that case.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=ZLH8JESd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52741-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com\n header.b=\"ZLH8JESd\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.162.69","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=nxp.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=nxp.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzVZC0nWjz1yGt\n\tfor ; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"quoted-printable","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n d3705802-af13-4504-379a-08de9e88c886","X-MS-Exchange-CrossTenant-originalarrivaltime":"20 Apr 2026 02:59:05.0082\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n UCJxq8a4NEDvQvCOcC6xQRuFGwni1BxfNHuoR9WjZibwfldgE9ztYYwlqW93s8E4tvS+FeYdkg476ADYC2qf7g==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AS8PR04MB7704"}},{"id":3679226,"web_url":"http://patchwork.ozlabs.org/comment/3679226/","msgid":"","list_archive_url":null,"date":"2026-04-20T05:59:37","subject":"Re: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","submitter":{"id":78905,"url":"http://patchwork.ozlabs.org/api/people/78905/","name":"Manivannan Sadhasivam","email":"mani@kernel.org"},"content":"On Fri, Apr 17, 2026 at 02:55:33PM -0500, Bjorn Helgaas wrote:\n> On Fri, Apr 17, 2026 at 03:17:16AM +0000, Sherry Sun wrote:\n> > > On Thu, Apr 16, 2026 at 07:14:12PM +0800, Sherry Sun wrote:\n> > > > Introduce generic helper functions to parse Root Port device\n> > > > tree nodes and extract common properties like reset GPIOs. This\n> > > > allows multiple PCI host controller drivers to share the same\n> > > > parsing logic.\n> > > >\n> > > > Define struct pci_host_port to hold common Root Port properties\n> > > > (currently only reset GPIO descriptor) and add\n> > > > pci_host_common_parse_ports() to parse Root Port nodes from\n> > > > device tree.\n> > > \n> > > Are the Root Port and the RC the only possible places for 'reset'\n> > > GPIO descriptions in DT? I think PERST# routing is outside the\n> > > PCIe spec, so it seems like a system could provide a PERST# GPIO\n> > > routed to any Switch Upstream Port or Endpoint (I assume a PERST#\n> > > connected to a switch would apply to both the upstream port and\n> > > the downstream ports).\n> > \n> > Thanks for the feedback. You're right that PERST# routing could\n> > theoretically be connected to any device in the hierarchy. However,\n> > for this patch series, I've focused on the most common use case in\n> > practice: use Root Port level PERST# instead of the legacy Root\n> > Complex level PERST#.\n> > \n> > Root Port level PERST# - This is the primary target, where each Root\n> > Port has individual control over devices connected to it. RC level\n> > PERST# - Legacy binding support, where a single GPIO controls all\n> > ports.\n> > \n> > We can extend this framework later if real hardware emerges that\n> > needs Switch or EP-level PERST# control. I can add a comment\n> > documenting this limitation if needed.\n> > \n> > BTW, Mani and Rob had some great discussions in dt-schema about\n> > PERST# and WAKE# sideband signals settings.\n> \n> > You can check here:\n> > https://github.com/devicetree-org/dt-schema/issues/168\n> > https://github.com/devicetree-org/dt-schema/pull/126\n> > https://github.com/devicetree-org/dt-schema/pull/170\n> \n> The upshot of all those conversations is that WAKE# and PERST# can be\n> routed to arbitrary devices independent of the PCI topology.\n> \n> I think extending host-generic to look for 'reset' in Root Port nodes\n> is the right thing. My concern is more about where we store it. This\n> patch saves it in a new \"pci_host_port\" struct, but someday we'll want\n> a place to save the PERST# GPIOs for several slots behind a switch.\n> Then we'll have two different ways to save the same information.\n> \n\nEven if there are PERST# GPIOs from the host, connected to downstream ports of a\nPCIe switch, they could be stored in the Root Port's (pci_host_port) struct as a\nlist of PERST#. This is what pcie-qcom driver does.\n\nIt is too clumsy to handle PERST# individually for each device. We tried it\nbefore with pwrctrl, but it always ended up biting us on who gets to control the\nPERST#. We can't let pwrctrl handle PERST# for a switch port and host controller\ndriver handle it for RP. And we cannot let pwrctrl handle PERST# for all ports,\nbecause, host controller drivers also need to control them for RC\ninitialization.\n\nThat's why it was decided to handle PERST# for all ports in the host controller\ndrivers. So following that pattern, this helper could also be extended to parse\nthe PERST# from all ports defined in DT and store them in the same Root Port\nstruct.\n\nIt should be trivial to implement this logic in the current helper. @Sherry:\nCould you please implement this logic?\n\n> WAKE# signals might be more pertinent -- we definitely need to support\n> multiple WAKE# signals below a single Root Port, and it seems like\n> PERST# and WAKE# GPIOs should be saved the same place.\n> \n> I'm wondering if both should go in the pci_dev itself. I guess the\n> implication is that a pci_dev->reset GPIO would describe a PERST#\n> connected to the device *below* the pci_dev, at least for Downstream\n> Ports.\n> \n\nProblem is, PERST# needs to be controlled even before 'pci_dev' gets created. We\ncreate 'pci_dev' only when a device get's detected. But the PERST# assertion and\ndeassertion happens even before the pci_host_probe() call, which is the starting\npoint for enumeration. That's why storing it as a list in 'pci_host_bridge'\nmakes it accessible by the host controller drivers.\n\n> I don't know about WAKE# signals. When it's in a connector, there's\n> probably only a single possible WAKE# per Downstream Port. But is it\n> possible have multiple WAKE# signals from a multi-function device\n> that's on the motherboard? Saving the WAKE# GPIO in the Downstream\n> Port wouldn't accommodate that case.\n\nAFAIK, a single device can have only one WAKE# irrespective of how many function\nit exposes. PCIe base spec doesn't indicate whether it is per-device or\nper-function, but the form factor specfications like CEM, Mini-CEM define it as\na per-device signal.\n\nMoreover, unlike PERST#, WAKE# is not driven by the host system. Host just needs\nto register an IRQ handler to service the interrupts raised by the device. So it\ncan be parsed *after* enumerating a device and stored in 'pci_dev' as done in\nKrishna's series:\nhttps://lore.kernel.org/linux-pci/20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com/\n\n- Mani","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=a70U5ES6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-52744-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"a70U5ES6\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzZZm0qVcz1yHB\n\tfor ; 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charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<20260417195533.GA92707@bhelgaas>"}},{"id":3679286,"web_url":"http://patchwork.ozlabs.org/comment/3679286/","msgid":"","list_archive_url":null,"date":"2026-04-20T08:24:57","subject":"RE: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"content":"> On Fri, Apr 17, 2026 at 02:55:33PM -0500, Bjorn Helgaas wrote:\n> > On Fri, Apr 17, 2026 at 03:17:16AM +0000, Sherry Sun wrote:\n> > > > On Thu, Apr 16, 2026 at 07:14:12PM +0800, Sherry Sun wrote:\n> > > > > Introduce generic helper functions to parse Root Port device\n> > > > > tree nodes and extract common properties like reset GPIOs. This\n> > > > > allows multiple PCI host controller drivers to share the same\n> > > > > parsing logic.\n> > > > >\n> > > > > Define struct pci_host_port to hold common Root Port properties\n> > > > > (currently only reset GPIO descriptor) and add\n> > > > > pci_host_common_parse_ports() to parse Root Port nodes from\n> > > > > device tree.\n> > > >\n> > > > Are the Root Port and the RC the only possible places for 'reset'\n> > > > GPIO descriptions in DT? I think PERST# routing is outside the\n> > > > PCIe spec, so it seems like a system could provide a PERST# GPIO\n> > > > routed to any Switch Upstream Port or Endpoint (I assume a PERST#\n> > > > connected to a switch would apply to both the upstream port and\n> > > > the downstream ports).\n> > >\n> > > Thanks for the feedback. You're right that PERST# routing could\n> > > theoretically be connected to any device in the hierarchy. However,\n> > > for this patch series, I've focused on the most common use case in\n> > > practice: use Root Port level PERST# instead of the legacy Root\n> > > Complex level PERST#.\n> > >\n> > > Root Port level PERST# - This is the primary target, where each Root\n> > > Port has individual control over devices connected to it. RC level\n> > > PERST# - Legacy binding support, where a single GPIO controls all\n> > > ports.\n> > >\n> > > We can extend this framework later if real hardware emerges that\n> > > needs Switch or EP-level PERST# control. I can add a comment\n> > > documenting this limitation if needed.\n> > >\n> > > BTW, Mani and Rob had some great discussions in dt-schema about\n> > > PERST# and WAKE# sideband signals settings.\n> >\n> > > You can check here:\n> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgi\n> > > thub.com%2Fdevicetree-org%2Fdt-\n> schema%2Fissues%2F168&data=05%7C02%7C\n> > >\n> sherry.sun%40nxp.com%7C232644f8bbe64279f77908de9ea20b09%7C686ea1\n> d3bc\n> > >\n> 2b4c6fa92cd99c5c301635%7C0%7C0%7C639122615977862858%7CUnknown\n> %7CTWFp\n> > >\n> bGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4z\n> MiIs\n> > >\n> IkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=r7szCLCsGFN2\n> 1ULZ\n> > > ibH7Ga%2FH0e6VyIdqznKCJ6yIGM4%3D&reserved=0\n> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgi\n> > > thub.com%2Fdevicetree-org%2Fdt-\n> schema%2Fpull%2F126&data=05%7C02%7Csh\n> > >\n> erry.sun%40nxp.com%7C232644f8bbe64279f77908de9ea20b09%7C686ea1d\n> 3bc2b\n> > >\n> 4c6fa92cd99c5c301635%7C0%7C0%7C639122615977892044%7CUnknown%7\n> CTWFpbG\n> > >\n> Zsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiI\n> sIk\n> > >\n> FOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=o3RIy1SfvTGfkX\n> 9rm8\n> > > dNH2or5SZ7v5bYF%2Fl1XGaf8aA%3D&reserved=0\n> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgi\n> > > thub.com%2Fdevicetree-org%2Fdt-\n> schema%2Fpull%2F170&data=05%7C02%7Csh\n> > >\n> erry.sun%40nxp.com%7C232644f8bbe64279f77908de9ea20b09%7C686ea1d\n> 3bc2b\n> > >\n> 4c6fa92cd99c5c301635%7C0%7C0%7C639122615977910169%7CUnknown%7\n> CTWFpbG\n> > >\n> Zsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiI\n> sIk\n> > >\n> FOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=d8SBGcqKcjYe1i\n> iqs9\n> > > %2F%2Bg1o%2FbECHYtnEULg7hTXyKmY%3D&reserved=0\n> >\n> > The upshot of all those conversations is that WAKE# and PERST# can be\n> > routed to arbitrary devices independent of the PCI topology.\n> >\n> > I think extending host-generic to look for 'reset' in Root Port nodes\n> > is the right thing. My concern is more about where we store it. This\n> > patch saves it in a new \"pci_host_port\" struct, but someday we'll want\n> > a place to save the PERST# GPIOs for several slots behind a switch.\n> > Then we'll have two different ways to save the same information.\n> >\n> \n> Even if there are PERST# GPIOs from the host, connected to downstream\n> ports of a PCIe switch, they could be stored in the Root Port's (pci_host_port)\n> struct as a list of PERST#. This is what pcie-qcom driver does.\n> \n> It is too clumsy to handle PERST# individually for each device. We tried it\n> before with pwrctrl, but it always ended up biting us on who gets to control\n> the PERST#. We can't let pwrctrl handle PERST# for a switch port and host\n> controller driver handle it for RP. And we cannot let pwrctrl handle PERST# for\n> all ports, because, host controller drivers also need to control them for RC\n> initialization.\n> \n> That's why it was decided to handle PERST# for all ports in the host controller\n> drivers. So following that pattern, this helper could also be extended to parse\n> the PERST# from all ports defined in DT and store them in the same Root Port\n> struct.\n> \n> It should be trivial to implement this logic in the current helper. @Sherry:\n> Could you please implement this logic?\n\nHi Mani, do you mean the similar logic in this patch?\nhttps://lore.kernel.org/all/20251216-pci-pwrctrl-rework-v2-1-745a563b9be6@oss.qualcomm.com/\nIf yes, of cause I can do this for current helper functions in pci-host-common.c.\n\nBest Regards\nSherry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=JlJhJRN0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 2487fc2e-cc3f-4d9e-ead6-08de9eb64eeb","X-MS-Exchange-CrossTenant-originalarrivaltime":"20 Apr 2026 08:24:57.8382\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n vC6LFQNy3CPucZp9szdDkyzRK4gnSk0zZhHSmYr4pvjSoNVwSxhXYKaHiyh69YFivuF/ua8zuI1j8eGV/hHs/w==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AS8PR04MB8900"}},{"id":3679325,"web_url":"http://patchwork.ozlabs.org/comment/3679325/","msgid":"","list_archive_url":null,"date":"2026-04-20T09:35:06","subject":"Re: [PATCH V13 02/12] PCI: host-generic: Add common helpers for\n parsing Root Port properties","submitter":{"id":78905,"url":"http://patchwork.ozlabs.org/api/people/78905/","name":"Manivannan Sadhasivam","email":"mani@kernel.org"},"content":"On Mon, Apr 20, 2026 at 08:24:57AM +0000, Sherry Sun wrote:\n\n[...]\n\n> > Even if there are PERST# GPIOs from the host, connected to downstream\n> > ports of a PCIe switch, they could be stored in the Root Port's (pci_host_port)\n> > struct as a list of PERST#. This is what pcie-qcom driver does.\n> > \n> > It is too clumsy to handle PERST# individually for each device. We tried it\n> > before with pwrctrl, but it always ended up biting us on who gets to control\n> > the PERST#. We can't let pwrctrl handle PERST# for a switch port and host\n> > controller driver handle it for RP. And we cannot let pwrctrl handle PERST# for\n> > all ports, because, host controller drivers also need to control them for RC\n> > initialization.\n> > \n> > That's why it was decided to handle PERST# for all ports in the host controller\n> > drivers. So following that pattern, this helper could also be extended to parse\n> > the PERST# from all ports defined in DT and store them in the same Root Port\n> > struct.\n> > \n> > It should be trivial to implement this logic in the current helper. @Sherry:\n> > Could you please implement this logic?\n> \n> Hi Mani, do you mean the similar logic in this patch?\n> https://lore.kernel.org/all/20251216-pci-pwrctrl-rework-v2-1-745a563b9be6@oss.qualcomm.com/\n> If yes, of cause I can do this for current helper functions in pci-host-common.c.\n> \n\nYes!\n\n- Mani","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=iV9s2VE7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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