[{"id":3678481,"web_url":"http://patchwork.ozlabs.org/comment/3678481/","msgid":"","list_archive_url":null,"date":"2026-04-17T05:03:17","subject":"Re: [PATCH v3 09/17] hw/usb/hcd-ehci: Implement 64-bit QH descriptor\n addressing","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 03:49, Jamin Lin wrote:\n> EHCI supports 64-bit control data structure addressing when the\n> 64-bit Addressing Capability bit in HCCPARAMS is set. In that mode,\n> the CTRLDSSEGMENT register supplies the upper 32 bits which are\n> concatenated with 32-bit link pointer fields to form full 64-bit\n> descriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n> \n> The current implementation assumes 32-bit QH descriptor addresses\n> and directly uses link pointer values without applying the\n> CTRLDSSEGMENT upper dword.\n> \n> Introduce a helper, ehci_get_desc_addr(), to construct full 64-bit\n> descriptor addresses when 64-bit capability is enabled. Update QH\n> traversal paths (async list walk, horizontal QH link, and periodic\n> schedule entry handling) to use the translated 64-bit addresses.\n> \n> EHCI 64-bit buffer pointer fields are defined in Appendix B as\n> split 32-bit low/high parts located at separate offsets, rather\n> than a single contiguous 64-bit field. Therefore, the buffer\n> pointers cannot be represented as uint64_t bufptr[5] without\n> violating the descriptor layout defined by the specification.\n> \n> Introduce ehci_get_buf_addr() to construct full 64-bit buffer\n> addresses from bufptr[] and bufptr_hi[] fields. Use this helper\n> when calculating transfer buffer addresses so that data buffers\n> above 4GB are correctly handled.\n> \n> Also add bufptr_hi[5] to EHCIqh to support 64-bit buffer pointer\n> fields as defined in Appendix B.\n> \n> When 64-bit capability is disabled, descriptor addresses remain\n> 32-bit and existing behaviour is unchanged.\n> \n> Note: Similar split 64-bit buffer pointer handling is required for\n> qTD, iTD and siTD descriptors, which will be addressed in follow-up\n> changes.\n> \n> Signed-off-by: Jamin Lin \n> ---\n> hw/usb/hcd-ehci.h | 4 ++++\n> hw/usb/hcd-ehci.c | 48 ++++++++++++++++++++++++++++++++++-----------\n> hw/usb/trace-events | 2 +-\n> 3 files changed, 42 insertions(+), 12 deletions(-)\n> \n> diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\n> index fe4c508c32..773f376834 100644\n> --- a/hw/usb/hcd-ehci.h\n> +++ b/hw/usb/hcd-ehci.h\n> @@ -141,6 +141,9 @@ typedef struct EHCIqtd {\n> #define QTD_BUFPTR_SH 12\n> } EHCIqtd;\n> \n> +/* QH overlay: altnext_qtd, token, bufptr[5], bufptr_hi[5] */\n> +#define EHCI_QH_OVERLAY_COUNT 12\n> +\n> /*\n> * EHCI spec version 1.0 Section 3.6\n> */\n> @@ -194,6 +197,7 @@ typedef struct EHCIqh {\n> #define BUFPTR_FRAMETAG_MASK 0x0000001f\n> #define BUFPTR_SBYTES_MASK 0x00000fe0\n> #define BUFPTR_SBYTES_SH 5\n> + uint32_t bufptr_hi[5];\n> } EHCIqh;\n> \n> enum async_state {\n> diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\n> index b9e4251d62..37ae637e08 100644\n> --- a/hw/usb/hcd-ehci.c\n> +++ b/hw/usb/hcd-ehci.c\n> @@ -147,6 +147,24 @@ static const char *addr2str(hwaddr addr)\n> return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);\n> }\n> \n> +static uint64_t ehci_get_buf_addr(EHCIState *s, uint32_t hi, uint32_t low,\n> + uint32_t mask)\n\nRename @mask as @low_mask? Or directly use 64-bit?\n\nstatic uint64_t ehci_get_buf_addr(const EHCIState *s,\n uint32_t hi, uint32_t lo,\n uint64_t mask)\n{\n uint64_t addr = s->caps_64bit_addr ? deposit64(lo, 0, 32, hi): lo;\n\n return addr & mask;\n}\n\n> +{\n> + uint64_t addr;\n> +\n> + addr = (uint64_t)(low & mask);\n> + if (s->caps_64bit_addr) {\n> + addr |= (uint64_t)hi << 32;\n> + }\n> +\n> + return addr;\n> +}\n> +\n> +static uint64_t ehci_get_desc_addr(EHCIState *s, uint32_t low)\n> +{\n> + return ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX);\n> +}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xHs17Qy5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxjVw4Q7Cz1yHp\n\tfor ; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::330;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678486,"web_url":"http://patchwork.ozlabs.org/comment/3678486/","msgid":"","list_archive_url":null,"date":"2026-04-17T05:40:10","subject":"RE: [PATCH v3 09/17] hw/usb/hcd-ehci: Implement 64-bit QH descriptor\n addressing","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"content":"Hi Philippe,\n\n> Subject: Re: [PATCH v3 09/17] hw/usb/hcd-ehci: Implement 64-bit QH\n> descriptor addressing\n> \n> On 16/4/26 03:49, Jamin Lin wrote:\n> > EHCI supports 64-bit control data structure addressing when the 64-bit\n> > Addressing Capability bit in HCCPARAMS is set. In that mode, the\n> > CTRLDSSEGMENT register supplies the upper 32 bits which are\n> > concatenated with 32-bit link pointer fields to form full 64-bit\n> > descriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n> >\n> > The current implementation assumes 32-bit QH descriptor addresses and\n> > directly uses link pointer values without applying the CTRLDSSEGMENT\n> > upper dword.\n> >\n> > Introduce a helper, ehci_get_desc_addr(), to construct full 64-bit\n> > descriptor addresses when 64-bit capability is enabled. Update QH\n> > traversal paths (async list walk, horizontal QH link, and periodic\n> > schedule entry handling) to use the translated 64-bit addresses.\n> >\n> > EHCI 64-bit buffer pointer fields are defined in Appendix B as split\n> > 32-bit low/high parts located at separate offsets, rather than a\n> > single contiguous 64-bit field. Therefore, the buffer pointers cannot\n> > be represented as uint64_t bufptr[5] without violating the descriptor\n> > layout defined by the specification.\n> >\n> > Introduce ehci_get_buf_addr() to construct full 64-bit buffer\n> > addresses from bufptr[] and bufptr_hi[] fields. Use this helper when\n> > calculating transfer buffer addresses so that data buffers above 4GB\n> > are correctly handled.\n> >\n> > Also add bufptr_hi[5] to EHCIqh to support 64-bit buffer pointer\n> > fields as defined in Appendix B.\n> >\n> > When 64-bit capability is disabled, descriptor addresses remain 32-bit\n> > and existing behaviour is unchanged.\n> >\n> > Note: Similar split 64-bit buffer pointer handling is required for\n> > qTD, iTD and siTD descriptors, which will be addressed in follow-up\n> > changes.\n> >\n> > Signed-off-by: Jamin Lin \n> > ---\n> > hw/usb/hcd-ehci.h | 4 ++++\n> > hw/usb/hcd-ehci.c | 48\n> ++++++++++++++++++++++++++++++++++-----------\n> > hw/usb/trace-events | 2 +-\n> > 3 files changed, 42 insertions(+), 12 deletions(-)\n> >\n> > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index\n> > fe4c508c32..773f376834 100644\n> > --- a/hw/usb/hcd-ehci.h\n> > +++ b/hw/usb/hcd-ehci.h\n> > @@ -141,6 +141,9 @@ typedef struct EHCIqtd {\n> > #define QTD_BUFPTR_SH 12\n> > } EHCIqtd;\n> >\n> > +/* QH overlay: altnext_qtd, token, bufptr[5], bufptr_hi[5] */ #define\n> > +EHCI_QH_OVERLAY_COUNT 12\n> > +\n> > /*\n> > * EHCI spec version 1.0 Section 3.6\n> > */\n> > @@ -194,6 +197,7 @@ typedef struct EHCIqh {\n> > #define BUFPTR_FRAMETAG_MASK 0x0000001f\n> > #define BUFPTR_SBYTES_MASK 0x00000fe0\n> > #define BUFPTR_SBYTES_SH 5\n> > + uint32_t bufptr_hi[5];\n> > } EHCIqh;\n> >\n> > enum async_state {\n> > diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index\n> > b9e4251d62..37ae637e08 100644\n> > --- a/hw/usb/hcd-ehci.c\n> > +++ b/hw/usb/hcd-ehci.c\n> > @@ -147,6 +147,24 @@ static const char *addr2str(hwaddr addr)\n> > return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names),\n> addr);\n> > }\n> >\n> > +static uint64_t ehci_get_buf_addr(EHCIState *s, uint32_t hi, uint32_t low,\n> > + uint32_t mask)\n> \n> Rename @mask as @low_mask? Or directly use 64-bit?\n> \n> static uint64_t ehci_get_buf_addr(const EHCIState *s,\n> uint32_t hi, uint32_t lo,\n> uint64_t mask) {\n> uint64_t addr = s->caps_64bit_addr ? deposit64(lo, 0, 32, hi): lo;\n> \n> return addr & mask;\n> }\n> \nThanks for the review and suggestion.\n\nIn the current code, the mask (e.g. QTD_BUFPTR_MASK) is defined as a 32-bit value and is intended to apply only to the low 32 bits of the buffer pointer.\nIf we change the function to take a 64-bit mask and apply it to the full 64-bit address (as in the proposed version), \nthe upper 32 bits (bits 63–32) may be unintentionally cleared when the mask is only 32-bit wide.\n\nFor example:\n\n#define QTD_BUFPTR_MASK 0xfffff000\n\nIn this case, applying \"addr & mask\" after combining hi/lo would zero out the high 32 bits, which breaks 64-bit addressing.\nTo preserve the original semantics, the mask should only be applied to the low part before combining with the high 32 bits.\nSo I suggest renaming the parameter to make this explicit. I will change this function as below. What do you think?\n\nstatic uint64_t ehci_get_buf_addr(EHCIState *s, uint32_t hi, uint32_t lo,\n uint32_t lo_mask)\n{\n uint64_t addr = lo & lo_mask;\n\n if (s->caps_64bit_addr) {\n addr = deposit64(addr, 32, 32, hi);\n }\n\n return addr;\n}\n\nThanks,\nJamin\n\n> > +{\n> > + uint64_t addr;\n> > +\n> > + addr = (uint64_t)(low & mask);\n> > + if (s->caps_64bit_addr) {\n> > + addr |= (uint64_t)hi << 32;\n> > + }\n> > +\n> > + return addr;\n> > +}\n> > +\n> > +static uint64_t ehci_get_desc_addr(EHCIState *s, uint32_t low) {\n> > + return ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX); }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=msPZBvQE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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In that mode, the\n>>> CTRLDSSEGMENT register supplies the upper 32 bits which are\n>>> concatenated with 32-bit link pointer fields to form full 64-bit\n>>> descriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n>>>\n>>> The current implementation assumes 32-bit QH descriptor addresses and\n>>> directly uses link pointer values without applying the CTRLDSSEGMENT\n>>> upper dword.\n>>>\n>>> Introduce a helper, ehci_get_desc_addr(), to construct full 64-bit\n>>> descriptor addresses when 64-bit capability is enabled. Update QH\n>>> traversal paths (async list walk, horizontal QH link, and periodic\n>>> schedule entry handling) to use the translated 64-bit addresses.\n>>>\n>>> EHCI 64-bit buffer pointer fields are defined in Appendix B as split\n>>> 32-bit low/high parts located at separate offsets, rather than a\n>>> single contiguous 64-bit field. Therefore, the buffer pointers cannot\n>>> be represented as uint64_t bufptr[5] without violating the descriptor\n>>> layout defined by the specification.\n>>>\n>>> Introduce ehci_get_buf_addr() to construct full 64-bit buffer\n>>> addresses from bufptr[] and bufptr_hi[] fields. Use this helper when\n>>> calculating transfer buffer addresses so that data buffers above 4GB\n>>> are correctly handled.\n>>>\n>>> Also add bufptr_hi[5] to EHCIqh to support 64-bit buffer pointer\n>>> fields as defined in Appendix B.\n>>>\n>>> When 64-bit capability is disabled, descriptor addresses remain 32-bit\n>>> and existing behaviour is unchanged.\n>>>\n>>> Note: Similar split 64-bit buffer pointer handling is required for\n>>> qTD, iTD and siTD descriptors, which will be addressed in follow-up\n>>> changes.\n>>>\n>>> Signed-off-by: Jamin Lin \n>>> ---\n>>> hw/usb/hcd-ehci.h | 4 ++++\n>>> hw/usb/hcd-ehci.c | 48\n>> ++++++++++++++++++++++++++++++++++-----------\n>>> hw/usb/trace-events | 2 +-\n>>> 3 files changed, 42 insertions(+), 12 deletions(-)\n\n\n>>> +static uint64_t ehci_get_buf_addr(EHCIState *s, uint32_t hi, uint32_t low,\n>>> + uint32_t mask)\n>>\n>> Rename @mask as @low_mask? Or directly use 64-bit?\n>>\n>> static uint64_t ehci_get_buf_addr(const EHCIState *s,\n>> uint32_t hi, uint32_t lo,\n>> uint64_t mask) {\n>> uint64_t addr = s->caps_64bit_addr ? deposit64(lo, 0, 32, hi): lo;\n>>\n>> return addr & mask;\n>> }\n>>\n> Thanks for the review and suggestion.\n> \n> In the current code, the mask (e.g. QTD_BUFPTR_MASK) is defined as a 32-bit value and is intended to apply only to the low 32 bits of the buffer pointer.\n> If we change the function to take a 64-bit mask and apply it to the full 64-bit address (as in the proposed version),\n> the upper 32 bits (bits 63–32) may be unintentionally cleared when the mask is only 32-bit wide.\n\nRight.\n\n> \n> For example:\n> \n> #define QTD_BUFPTR_MASK 0xfffff000\n> \n> In this case, applying \"addr & mask\" after combining hi/lo would zero out the high 32 bits, which breaks 64-bit addressing.\n> To preserve the original semantics, the mask should only be applied to the low part before combining with the high 32 bits.\n> So I suggest renaming the parameter to make this explicit. I will change this function as below. What do you think?\n> \n> static uint64_t ehci_get_buf_addr(\n\n\"const\"\n\nEHCIState *s, uint32_t hi, uint32_t lo,\n> uint32_t lo_mask)\n> {\n> uint64_t addr = lo & lo_mask;\n> \n> if (s->caps_64bit_addr) {\n> addr = deposit64(addr, 32, 32, hi);\n> }\n> \n> return addr;\n> }\nPerfect, using \"const\":\n\nReviewed-by: Philippe Mathieu-Daudé ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Sywxd6xe;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxl3W3VBgz1yHp\n\tfor ; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678523,"web_url":"http://patchwork.ozlabs.org/comment/3678523/","msgid":"","list_archive_url":null,"date":"2026-04-17T07:02:24","subject":"RE: [PATCH v3 09/17] hw/usb/hcd-ehci: Implement 64-bit QH descriptor\n addressing","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"content":"Hi Philippe,\n\n> Subject: Re: [PATCH v3 09/17] hw/usb/hcd-ehci: Implement 64-bit QH\n> descriptor addressing\n> \n> On 17/4/26 07:40, Jamin Lin wrote:\n> > Hi Philippe,\n> >\n> >> Subject: Re: [PATCH v3 09/17] hw/usb/hcd-ehci: Implement 64-bit QH\n> >> descriptor addressing\n> >>\n> >> On 16/4/26 03:49, Jamin Lin wrote:\n> >>> EHCI supports 64-bit control data structure addressing when the\n> >>> 64-bit Addressing Capability bit in HCCPARAMS is set. In that mode,\n> >>> the CTRLDSSEGMENT register supplies the upper 32 bits which are\n> >>> concatenated with 32-bit link pointer fields to form full 64-bit\n> >>> descriptor addresses (EHCI 1.0, section 2.3.5 and Appendix B).\n> >>>\n> >>> The current implementation assumes 32-bit QH descriptor addresses\n> >>> and directly uses link pointer values without applying the\n> >>> CTRLDSSEGMENT upper dword.\n> >>>\n> >>> Introduce a helper, ehci_get_desc_addr(), to construct full 64-bit\n> >>> descriptor addresses when 64-bit capability is enabled. Update QH\n> >>> traversal paths (async list walk, horizontal QH link, and periodic\n> >>> schedule entry handling) to use the translated 64-bit addresses.\n> >>>\n> >>> EHCI 64-bit buffer pointer fields are defined in Appendix B as split\n> >>> 32-bit low/high parts located at separate offsets, rather than a\n> >>> single contiguous 64-bit field. Therefore, the buffer pointers\n> >>> cannot be represented as uint64_t bufptr[5] without violating the\n> >>> descriptor layout defined by the specification.\n> >>>\n> >>> Introduce ehci_get_buf_addr() to construct full 64-bit buffer\n> >>> addresses from bufptr[] and bufptr_hi[] fields. Use this helper when\n> >>> calculating transfer buffer addresses so that data buffers above 4GB\n> >>> are correctly handled.\n> >>>\n> >>> Also add bufptr_hi[5] to EHCIqh to support 64-bit buffer pointer\n> >>> fields as defined in Appendix B.\n> >>>\n> >>> When 64-bit capability is disabled, descriptor addresses remain\n> >>> 32-bit and existing behaviour is unchanged.\n> >>>\n> >>> Note: Similar split 64-bit buffer pointer handling is required for\n> >>> qTD, iTD and siTD descriptors, which will be addressed in follow-up\n> >>> changes.\n> >>>\n> >>> Signed-off-by: Jamin Lin \n> >>> ---\n> >>> hw/usb/hcd-ehci.h | 4 ++++\n> >>> hw/usb/hcd-ehci.c | 48\n> >> ++++++++++++++++++++++++++++++++++-----------\n> >>> hw/usb/trace-events | 2 +-\n> >>> 3 files changed, 42 insertions(+), 12 deletions(-)\n> \n> \n> >>> +static uint64_t ehci_get_buf_addr(EHCIState *s, uint32_t hi, uint32_t low,\n> >>> + uint32_t mask)\n> >>\n> >> Rename @mask as @low_mask? Or directly use 64-bit?\n> >>\n> >> static uint64_t ehci_get_buf_addr(const EHCIState *s,\n> >> uint32_t hi, uint32_t lo,\n> >> uint64_t mask) {\n> >> uint64_t addr = s->caps_64bit_addr ? deposit64(lo, 0, 32, hi):\n> >> lo;\n> >>\n> >> return addr & mask;\n> >> }\n> >>\n> > Thanks for the review and suggestion.\n> >\n> > In the current code, the mask (e.g. QTD_BUFPTR_MASK) is defined as a\n> 32-bit value and is intended to apply only to the low 32 bits of the buffer\n> pointer.\n> > If we change the function to take a 64-bit mask and apply it to the\n> > full 64-bit address (as in the proposed version), the upper 32 bits (bits 63–32)\n> may be unintentionally cleared when the mask is only 32-bit wide.\n> \n> Right.\n> \n> >\n> > For example:\n> >\n> > #define QTD_BUFPTR_MASK 0xfffff000\n> >\n> > In this case, applying \"addr & mask\" after combining hi/lo would zero out the\n> high 32 bits, which breaks 64-bit addressing.\n> > To preserve the original semantics, the mask should only be applied to the\n> low part before combining with the high 32 bits.\n> > So I suggest renaming the parameter to make this explicit. I will change this\n> function as below. What do you think?\n> >\n> > static uint64_t ehci_get_buf_addr(\n> \n> \"const\"\n> \n\n\nThanks for the suggestion.\nWill add.\nJamin\n\n> EHCIState *s, uint32_t hi, uint32_t lo,\n> > uint32_t lo_mask) {\n> > uint64_t addr = lo & lo_mask;\n> >\n> > if (s->caps_64bit_addr) {\n> > addr = deposit64(addr, 32, 32, hi);\n> > }\n> >\n> > return addr;\n> > }\n> Perfect, using \"const\":\n> \n> Reviewed-by: Philippe Mathieu-Daudé ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=DH6Zejp0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=aspeedtech.com;"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxm6t6sFsz1yD3\n\tfor ; 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