[{"id":3678500,"web_url":"http://patchwork.ozlabs.org/comment/3678500/","msgid":"<6b535f08-8ee8-4227-9dfb-3d4914d825bf@linaro.org>","list_archive_url":null,"date":"2026-04-17T06:23:35","subject":"Re: [PATCH v3 13/17] hw/usb/hcd-ehci: Add descriptor address offset\n property","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 03:49, Jamin Lin wrote:\n> When 64-bit addressing is supported, the Linux EHCI driver programs the\n> segment register to zero. See ehci_run function:\n> https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-hcd.c\n> \n> The driver comment also notes that descriptor structures allocated from\n> the DMA pool use segment zero semantics.\n> \n> Descriptor memory is allocated using the DMA API. The platform driver\n> configures a 64-bit DMA mask so memory can be allocated above 4GB.\n> See ehci_platform_probe function:\n> https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-platform.c\n> \n> On AST2700 platforms, system DRAM is mapped above 4GB at 0x400000000.\n> As a result, descriptor addresses constructed directly from the guest\n> EHCI registers do not match the actual system address used by the\n> controller when fetching queue heads (QH) and queue element transfer\n> descriptors (qTD).\n> \n> Introduce a descriptor-addr-offset property so platforms can provide an\n> address offset applied when constructing descriptor addresses. This\n> allows systems where DRAM resides above 4GB to correctly access EHCI\n> descriptors while keeping the default behavior unchanged for existing\n> machines.\n> \n> Signed-off-by: Jamin Lin \n> ---\n> hw/usb/hcd-ehci.h | 1 +\n> hw/usb/hcd-ehci-pci.c | 2 ++\n> hw/usb/hcd-ehci-sysbus.c | 2 ++\n> hw/usb/hcd-ehci.c | 7 ++++++-\n> 4 files changed, 11 insertions(+), 1 deletion(-)\n> \n> diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\n> index 6406f536e8..05d8db4a5d 100644\n> --- a/hw/usb/hcd-ehci.h\n> +++ b/hw/usb/hcd-ehci.h\n> @@ -264,6 +264,7 @@ struct EHCIState {\n> /* properties */\n> uint32_t maxframes;\n> bool caps_64bit_addr;\n> + uint64_t descriptor_addr_offset;\n\nI note OHCI uses \"dma_addr_t dma_offset;\" here.\n\n> \n> /*\n> * EHCI spec version 1.0 Section 2.3\n> diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c\n> index 2ea8549db9..115d05ede0 100644\n> --- a/hw/usb/hcd-ehci-pci.c\n> +++ b/hw/usb/hcd-ehci-pci.c\n> @@ -139,6 +139,8 @@ static const Property ehci_pci_properties[] = {\n> DEFINE_PROP_UINT32(\"maxframes\", EHCIPCIState, ehci.maxframes, 128),\n> DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCIPCIState, ehci.caps_64bit_addr,\n> false),\n> + DEFINE_PROP_UINT64(\"descriptor-addr-offset\", EHCIPCIState,\n> + ehci.descriptor_addr_offset, 0),\n> };\n\nI note OHCI uses DEFINE_PROP_DMAADDR() here. Single use, maybe better\nremove it and stick to uint64_t as you use.\n\n\nCould we have a DEFINE_EHCI_COMMON_PROPERTIES() macro for common\nentries instead, such DEFINE_SDHCI_COMMON_PROPERTIES()?\n\n> \n> static const VMStateDescription vmstate_ehci_pci = {\n> diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c\n> index 61215e9f3d..df138fb339 100644\n> --- a/hw/usb/hcd-ehci-sysbus.c\n> +++ b/hw/usb/hcd-ehci-sysbus.c\n> @@ -36,6 +36,8 @@ static const Property ehci_sysbus_properties[] = {\n> false),\n> DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCISysBusState, ehci.caps_64bit_addr,\n> false),\n> + DEFINE_PROP_UINT64(\"descriptor-addr-offset\", EHCISysBusState,\n> + ehci.descriptor_addr_offset, 0),\n> };","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=h+cQ+4LZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678517,"web_url":"http://patchwork.ozlabs.org/comment/3678517/","msgid":"<04a8d8d9-f605-4bd3-8468-0e2840ae8311@kaod.org>","list_archive_url":null,"date":"2026-04-17T06:45:33","subject":"Re: [PATCH v3 13/17] hw/usb/hcd-ehci: Add descriptor address offset\n property","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/","name":"Cédric Le Goater","email":"clg@kaod.org"},"content":"On 4/16/26 03:49, Jamin Lin wrote:\n> When 64-bit addressing is supported, the Linux EHCI driver programs the\n> segment register to zero. See ehci_run function:\n> https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-hcd.c\n> \n> The driver comment also notes that descriptor structures allocated from\n> the DMA pool use segment zero semantics.\n> \n> Descriptor memory is allocated using the DMA API. The platform driver\n> configures a 64-bit DMA mask so memory can be allocated above 4GB.\n> See ehci_platform_probe function:\n> https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-platform.c\n> \n> On AST2700 platforms, system DRAM is mapped above 4GB at 0x400000000.\n> As a result, descriptor addresses constructed directly from the guest\n> EHCI registers do not match the actual system address used by the\n> controller when fetching queue heads (QH) and queue element transfer\n> descriptors (qTD).\n> \n> Introduce a descriptor-addr-offset property so platforms can provide an\n> address offset applied when constructing descriptor addresses. This\n> allows systems where DRAM resides above 4GB to correctly access EHCI\n> descriptors while keeping the default behavior unchanged for existing\n> machines.\n> \n> Signed-off-by: Jamin Lin \n> ---\n> hw/usb/hcd-ehci.h | 1 +\n> hw/usb/hcd-ehci-pci.c | 2 ++\n> hw/usb/hcd-ehci-sysbus.c | 2 ++\n> hw/usb/hcd-ehci.c | 7 ++++++-\n> 4 files changed, 11 insertions(+), 1 deletion(-)\n> \n> diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\n> index 6406f536e8..05d8db4a5d 100644\n> --- a/hw/usb/hcd-ehci.h\n> +++ b/hw/usb/hcd-ehci.h\n> @@ -264,6 +264,7 @@ struct EHCIState {\n> /* properties */\n> uint32_t maxframes;\n> bool caps_64bit_addr;\n> + uint64_t descriptor_addr_offset;\n> \n> /*\n> * EHCI spec version 1.0 Section 2.3\n> diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c\n> index 2ea8549db9..115d05ede0 100644\n> --- a/hw/usb/hcd-ehci-pci.c\n> +++ b/hw/usb/hcd-ehci-pci.c\n> @@ -139,6 +139,8 @@ static const Property ehci_pci_properties[] = {\n> DEFINE_PROP_UINT32(\"maxframes\", EHCIPCIState, ehci.maxframes, 128),\n> DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCIPCIState, ehci.caps_64bit_addr,\n> false),\n> + DEFINE_PROP_UINT64(\"descriptor-addr-offset\", EHCIPCIState,\n> + ehci.descriptor_addr_offset, 0),\n> };\n> \n> static const VMStateDescription vmstate_ehci_pci = {\n> diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c\n> index 61215e9f3d..df138fb339 100644\n> --- a/hw/usb/hcd-ehci-sysbus.c\n> +++ b/hw/usb/hcd-ehci-sysbus.c\n> @@ -36,6 +36,8 @@ static const Property ehci_sysbus_properties[] = {\n> false),\n> DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCISysBusState, ehci.caps_64bit_addr,\n> false),\n> + DEFINE_PROP_UINT64(\"descriptor-addr-offset\", EHCISysBusState,\n> + ehci.descriptor_addr_offset, 0),\n> };\n> \n> static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)\n> diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\n> index e1d5ecbad7..ea9d5846bc 100644\n> --- a/hw/usb/hcd-ehci.c\n> +++ b/hw/usb/hcd-ehci.c\n> @@ -162,7 +162,12 @@ static uint64_t ehci_get_buf_addr(EHCIState *s, uint32_t hi, uint32_t low,\n> \n> static uint64_t ehci_get_desc_addr(EHCIState *s, uint32_t low)\n> {\n> - return ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX);\n> + uint64_t addr;\n> +\n> + addr = ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX);\n> + addr += s->descriptor_addr_offset;\n\n\nInstead, can we force a default value for ctrldssegment when\ncaps_64bit_addr is set ?\n\nI am still trying to digest :\n\n https://lore.kernel.org/qemu-devel/TYPPR06MB8206C7461E004C4FF07B8E92FC242@TYPPR06MB8206.apcprd06.prod.outlook.com/\n\nWe have time let's take a moment to think about the workaround.\n\nThanks,\n\nC.\n\n> + return addr;\n> }\n> \n> static void ehci_trace_usbsts(uint32_t mask, int state)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kaod.org header.i=@kaod.org header.a=rsa-sha256\n header.s=ovhmo393970-selector1 header.b=FwojPpey;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","garm.ovh; auth=pass\n (GARM-97G002d42f6607-83c0-44b0-99eb-82df27182ee8,\n AF90ED76F5B1EEBCDFB51C8C68949B04E112CC0D) smtp.auth=clg@kaod.org"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxlm223wmz1yD3\n\tfor ; Fri, 17 Apr 2026 16:46:40 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDcxg-00014o-QE; Fri, 17 Apr 2026 02:45:56 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wDcxW-00014M-GD\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 02:45:47 -0400","from 11.mo534.mail-out.ovh.net ([46.105.33.174])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wDcxR-0002an-AA\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 02:45:46 -0400","from director5.derp.mail-out.ovh.net\n (director5.derp.mail-out.ovh.net [51.68.94.138])\n by mo534.mail-out.ovh.net (Postfix) with ESMTPS id 4fxlkm1rpFz6LvL;\n Fri, 17 Apr 2026 06:45:35 +0000 (UTC)","from director5.derp.mail-out.ovh.net\n (director5.derp.mail-out.ovh.net. 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See ehci_run function:\n>> https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-hcd.c\n>>\n>> The driver comment also notes that descriptor structures allocated from\n>> the DMA pool use segment zero semantics.\n>>\n>> Descriptor memory is allocated using the DMA API. The platform driver\n>> configures a 64-bit DMA mask so memory can be allocated above 4GB.\n>> See ehci_platform_probe function:\n>> https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci- \n>> platform.c\n>>\n>> On AST2700 platforms, system DRAM is mapped above 4GB at 0x400000000.\n>> As a result, descriptor addresses constructed directly from the guest\n>> EHCI registers do not match the actual system address used by the\n>> controller when fetching queue heads (QH) and queue element transfer\n>> descriptors (qTD).\n>>\n>> Introduce a descriptor-addr-offset property so platforms can provide an\n>> address offset applied when constructing descriptor addresses. This\n>> allows systems where DRAM resides above 4GB to correctly access EHCI\n>> descriptors while keeping the default behavior unchanged for existing\n>> machines.\n>>\n>> Signed-off-by: Jamin Lin \n>> ---\n>>   hw/usb/hcd-ehci.h        | 1 +\n>>   hw/usb/hcd-ehci-pci.c    | 2 ++\n>>   hw/usb/hcd-ehci-sysbus.c | 2 ++\n>>   hw/usb/hcd-ehci.c        | 7 ++++++-\n>>   4 files changed, 11 insertions(+), 1 deletion(-)\n\n\n>> diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\n>> index e1d5ecbad7..ea9d5846bc 100644\n>> --- a/hw/usb/hcd-ehci.c\n>> +++ b/hw/usb/hcd-ehci.c\n>> @@ -162,7 +162,12 @@ static uint64_t ehci_get_buf_addr(EHCIState *s, \n>> uint32_t hi, uint32_t low,\n>>   static uint64_t ehci_get_desc_addr(EHCIState *s, uint32_t low)\n>>   {\n>> -    return ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX);\n>> +    uint64_t addr;\n>> +\n>> +    addr = ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX);\n>> +    addr += s->descriptor_addr_offset;\n> \n> \n> Instead, can we force a default value for ctrldssegment when\n> caps_64bit_addr is set ?\n> \n> I am still trying to digest :\n> \n>   https://lore.kernel.org/qemu-devel/ \n> TYPPR06MB8206C7461E004C4FF07B8E92FC242@TYPPR06MB8206.apcprd06.prod.outlook.com/\n\nSame here, but since it doesn't break and I don't have much more time\nto dedicate to this I ended thinking \"good enough for now, could be\nimproved later\", so no objection on my side.\n\n> \n> We have time let's take a moment to think about the workaround.\n\nThen keep me in the loop!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=SWIcIBM6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::331;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3679223,"web_url":"http://patchwork.ozlabs.org/comment/3679223/","msgid":"","list_archive_url":null,"date":"2026-04-20T05:47:45","subject":"RE: [PATCH v3 13/17] hw/usb/hcd-ehci: Add descriptor address offset\n property","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"content":"Hi Philippe, Cédric\n\n> >> -    return ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX);\n> >> +    uint64_t addr;\n> >> +\n> >> +    addr = ehci_get_buf_addr(s, s->ctrldssegment, low, UINT32_MAX);\n> >> +    addr += s->descriptor_addr_offset;\n> >\n> >\n> > Instead, can we force a default value for ctrldssegment when\n> > caps_64bit_addr is set ?\n> >\n> > I am still trying to digest :\n> >\n> >   https://lore.kernel.org/qemu-devel/\n> >\n> TYPPR06MB8206C7461E004C4FF07B8E92FC242@TYPPR06MB8206.apcprd06.\n> prod.out\n> > look.com/\n> \n> Same here, but since it doesn't break and I don't have much more time to\n> dedicate to this I ended thinking \"good enough for now, could be improved\n> later\", so no objection on my side.\n> \n> >\n> > We have time let's take a moment to think about the workaround.\n> \n> Then keep me in the loop!\n\n\nThanks for the review and the suggestion.\n\nI tried to address this by introducing a new property:\naspeed-ast2700-workaround.\n\nWhen this property is enabled:\n\n1. We force bit 2 of the CTRLDSSEGMENT register to 1 during initialization (when caps_64bit_addr is set).\n2. Additionally, if firmware writes to the CTRLDSSEGMENT register, we also ensure that bit 2 remains set.\n\nThis keeps the behavior contained to AST2700-specific usage and avoids impacting other platforms.\nLet me know if you think this approach makes sense, or if you'd prefer a different direction.\n\nJamin\n\ndiff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\nindex af8c080c60..0a58dca668 100644\n--- a/hw/usb/hcd-ehci.h\n+++ b/hw/usb/hcd-ehci.h\n@@ -263,6 +263,7 @@ struct EHCIState {\n /* properties */\n uint32_t maxframes;\n bool caps_64bit_addr;\n+ bool aspeed_ast2700_workaround;\n\n /*\n * EHCI spec version 1.0 Section 2.3\ndiff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c\nindex 4a1f7cad73..83114bae90 100644\n--- a/hw/arm/aspeed_ast27x0.c\n+++ b/hw/arm/aspeed_ast27x0.c\n@@ -858,6 +858,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n for (i = 0; i < sc->ehcis_num; i++) {\n object_property_set_bool(OBJECT(&s->ehci[i]), \"caps-64bit-addr\", true,\n &error_abort);\n+ object_property_set_bool(OBJECT(&s->ehci[i]),\n+ \"aspeed-ast2700-workaround\", true,\n+ &error_abort);\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {\n return;\n }\ndiff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c\nindex 61215e9f3d..01f72a5a1e 100644\n--- a/hw/usb/hcd-ehci-sysbus.c\n+++ b/hw/usb/hcd-ehci-sysbus.c\n@@ -36,6 +36,9 @@ static const Property ehci_sysbus_properties[] = {\n false),\n DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCISysBusState, ehci.caps_64bit_addr,\n false),\n+ DEFINE_PROP_BOOL(\"aspeed-ast2700-workaround\", EHCISysBusState,\n+ ehci.aspeed_ast2700_workaround,\n+ false),\n };\n\n static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)\ndiff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\nindex 7f90fd119d..403d7e84a7 100644\n--- a/hw/usb/hcd-ehci.c\n+++ b/hw/usb/hcd-ehci.c\n@@ -1133,6 +1133,9 @@ static void ehci_opreg_write(void *ptr, hwaddr addr,\n \" 64-bit addressing capability is disabled\\n\");\n return;\n }\n+ if (s->aspeed_ast2700_workaround) {\n+ val |= BIT(2);\n+ }\n break;\n case ASYNCLISTADDR:\n if (ehci_async_enabled(s)) {\n@@ -2582,6 +2585,9 @@ void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)\n }\n if (s->caps_64bit_addr) {\n s->caps[0x08] |= BIT(0);\n+ if (s->aspeed_ast2700_workaround) {\n+ s->ctrldssegment |= BIT(2);\n+ }\n }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=EDXB4N8o;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Perhaps \"ctrldssegment-default\", as a uint32_t,\nwhich defaults to 0x0 and when the ast2700 SoC is realized,\nset to BIT(2).\n\n\n> \n> When this property is enabled:\n> \n> 1. We force bit 2 of the CTRLDSSEGMENT register to 1 during initialization (when caps_64bit_addr is set).\n> 2. Additionally, if firmware writes to the CTRLDSSEGMENT register, we also ensure that bit 2 remains set.\n> \n> This keeps the behavior contained to AST2700-specific usage and avoids impacting other platforms.\n> Let me know if you think this approach makes sense, or if you'd prefer a different direction.\n> \n> Jamin\n> \n> diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h\n> index af8c080c60..0a58dca668 100644\n> --- a/hw/usb/hcd-ehci.h\n> +++ b/hw/usb/hcd-ehci.h\n> @@ -263,6 +263,7 @@ struct EHCIState {\n> /* properties */\n> uint32_t maxframes;\n> bool caps_64bit_addr;\n> + bool aspeed_ast2700_workaround;\n> \n> /*\n> * EHCI spec version 1.0 Section 2.3\n> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c\n> index 4a1f7cad73..83114bae90 100644\n> --- a/hw/arm/aspeed_ast27x0.c\n> +++ b/hw/arm/aspeed_ast27x0.c\n> @@ -858,6 +858,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n> for (i = 0; i < sc->ehcis_num; i++) {\n> object_property_set_bool(OBJECT(&s->ehci[i]), \"caps-64bit-addr\", true,\n> &error_abort);\n> + object_property_set_bool(OBJECT(&s->ehci[i]),\n> + \"aspeed-ast2700-workaround\", true,\n> + &error_abort);\n> if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {\n> return;\n> }\n> diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c\n> index 61215e9f3d..01f72a5a1e 100644\n> --- a/hw/usb/hcd-ehci-sysbus.c\n> +++ b/hw/usb/hcd-ehci-sysbus.c\n> @@ -36,6 +36,9 @@ static const Property ehci_sysbus_properties[] = {\n> false),\n> DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCISysBusState, ehci.caps_64bit_addr,\n> false),\n> + DEFINE_PROP_BOOL(\"aspeed-ast2700-workaround\", EHCISysBusState,\n> + ehci.aspeed_ast2700_workaround,\n> + false),\n> };\n> \n> static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)\n> diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c\n> index 7f90fd119d..403d7e84a7 100644\n> --- a/hw/usb/hcd-ehci.c\n> +++ b/hw/usb/hcd-ehci.c\n> @@ -1133,6 +1133,9 @@ static void ehci_opreg_write(void *ptr, hwaddr addr,\n> \" 64-bit addressing capability is disabled\\n\");\n> return;\n> }\n> + if (s->aspeed_ast2700_workaround) {\n> + val |= BIT(2);\n> + }\n\nWith the proposal above, this would be changed to :\n\n\tval |= s->ctrldssegment_default;\n\n> break;\n> case ASYNCLISTADDR:\n> if (ehci_async_enabled(s)) {\n> @@ -2582,6 +2585,9 @@ void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)\n> }\n> if (s->caps_64bit_addr) {\n> s->caps[0x08] |= BIT(0);\n> + if (s->aspeed_ast2700_workaround) {\n> + s->ctrldssegment |= BIT(2);\n\nShouldn't these assignments be in the reset handlers ?\n\nThanks,\n\nC.\n\n\n> + }\n> }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kaod.org header.i=@kaod.org header.a=rsa-sha256\n header.s=ovhmo393970-selector1 header.b=krJixErk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","garm.ovh; auth=pass\n (GARM-98R00207c970ca-cd83-4aaf-bee3-afe8e999efe3,\n EAA5D49A92D75878AB6B5DB8F91ADF3A5E4E180D) smtp.auth=clg@kaod.org"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzc7b35m7z1yD4\n\tfor ; Mon, 20 Apr 2026 17:10:01 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wEikv-0003ot-JF; Mon, 20 Apr 2026 03:09:18 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wEikk-0003mF-T8\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 03:09:08 -0400","from 11.mo534.mail-out.ovh.net ([46.105.33.174])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from ) id 1wEikh-0003Xa-Lq\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 03:09:06 -0400","from director4.derp.mail-out.ovh.net\n (director4.derp.mail-out.ovh.net [79.137.60.37])\n by mo534.mail-out.ovh.net (Postfix) with ESMTPS id 4fzc686vv0z67hc;\n Mon, 20 Apr 2026 07:08:48 +0000 (UTC)","from director4.derp.mail-out.ovh.net\n (director4.derp.mail-out.ovh.net. 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See ehci_run function:\n> > https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-hc\n> > d.c\n> >\n> > The driver comment also notes that descriptor structures allocated\n> > from the DMA pool use segment zero semantics.\n> >\n> > Descriptor memory is allocated using the DMA API. The platform driver\n> > configures a 64-bit DMA mask so memory can be allocated above 4GB.\n> > See ehci_platform_probe function:\n> > https://github.com/torvalds/linux/blob/master/drivers/usb/host/ehci-pl\n> > atform.c\n> >\n> > On AST2700 platforms, system DRAM is mapped above 4GB at\n> 0x400000000.\n> > As a result, descriptor addresses constructed directly from the guest\n> > EHCI registers do not match the actual system address used by the\n> > controller when fetching queue heads (QH) and queue element transfer\n> > descriptors (qTD).\n> >\n> > Introduce a descriptor-addr-offset property so platforms can provide\n> > an address offset applied when constructing descriptor addresses. This\n> > allows systems where DRAM resides above 4GB to correctly access EHCI\n> > descriptors while keeping the default behavior unchanged for existing\n> > machines.\n> >\n> > Signed-off-by: Jamin Lin \n> > ---\n> > hw/usb/hcd-ehci.h | 1 +\n> > hw/usb/hcd-ehci-pci.c | 2 ++\n> > hw/usb/hcd-ehci-sysbus.c | 2 ++\n> > hw/usb/hcd-ehci.c | 7 ++++++-\n> > 4 files changed, 11 insertions(+), 1 deletion(-)\n> >\n> > diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index\n> > 6406f536e8..05d8db4a5d 100644\n> > --- a/hw/usb/hcd-ehci.h\n> > +++ b/hw/usb/hcd-ehci.h\n> > @@ -264,6 +264,7 @@ struct EHCIState {\n> > /* properties */\n> > uint32_t maxframes;\n> > bool caps_64bit_addr;\n> > + uint64_t descriptor_addr_offset;\n> \n> I note OHCI uses \"dma_addr_t dma_offset;\" here.\n> \n> >\n> > /*\n> > * EHCI spec version 1.0 Section 2.3 diff --git\n> > a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c index\n> > 2ea8549db9..115d05ede0 100644\n> > --- a/hw/usb/hcd-ehci-pci.c\n> > +++ b/hw/usb/hcd-ehci-pci.c\n> > @@ -139,6 +139,8 @@ static const Property ehci_pci_properties[] = {\n> > DEFINE_PROP_UINT32(\"maxframes\", EHCIPCIState, ehci.maxframes,\n> 128),\n> > DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCIPCIState,\n> ehci.caps_64bit_addr,\n> > false),\n> > + DEFINE_PROP_UINT64(\"descriptor-addr-offset\", EHCIPCIState,\n> > + ehci.descriptor_addr_offset, 0),\n> > };\n> \n> I note OHCI uses DEFINE_PROP_DMAADDR() here. Single use, maybe better\n> remove it and stick to uint64_t as you use.\n> \nThanks for the suggestion and review.\n\nBased on Cédric’s feedback, I will update the ctrldssegment-default property to use a uint32_t type.\n\n> \n> Could we have a DEFINE_EHCI_COMMON_PROPERTIES() macro for common\n> entries instead, such DEFINE_SDHCI_COMMON_PROPERTIES()?\n>\n\nWill do\n\nThanks,\nJamin\n \n> >\n> > static const VMStateDescription vmstate_ehci_pci = { diff --git\n> > a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index\n> > 61215e9f3d..df138fb339 100644\n> > --- a/hw/usb/hcd-ehci-sysbus.c\n> > +++ b/hw/usb/hcd-ehci-sysbus.c\n> > @@ -36,6 +36,8 @@ static const Property ehci_sysbus_properties[] = {\n> > false),\n> > DEFINE_PROP_BOOL(\"caps-64bit-addr\", EHCISysBusState,\n> ehci.caps_64bit_addr,\n> > false),\n> > + DEFINE_PROP_UINT64(\"descriptor-addr-offset\", EHCISysBusState,\n> > + ehci.descriptor_addr_offset, 0),\n> > };\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=gZgAikxW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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