[{"id":3678499,"web_url":"http://patchwork.ozlabs.org/comment/3678499/","msgid":"<7ec734f8-4b9d-428d-87f9-89c87d54956f@linaro.org>","list_archive_url":null,"date":"2026-04-17T06:23:48","subject":"Re: [PATCH v3 14/17] hw/arm/aspeed_ast27x0: Enable 64-bit EHCI DMA\n addressing","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 03:50, Jamin Lin wrote:\n> AST2700 supports a 64-bit DRAM address space. Therefore, DMA\n> transactions must be capable of accessing 64-bit addresses.\n> \n> Enable the \"caps-64bit-addr\" property for the EHCI controllers\n> on AST2700 so that USB DMA operations can correctly handle\n> 64-bit memory addresses.\n> \n> Signed-off-by: Jamin Lin \n> Reviewed-by: Cédric Le Goater \n> ---\n> hw/arm/aspeed_ast27x0.c | 2 ++\n> 1 file changed, 2 insertions(+)\n\nReviewed-by: Philippe Mathieu-Daudé ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ByuXGAt/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxlGf6zBnz1yHp\n\tfor ; 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