[{"id":3678501,"web_url":"http://patchwork.ozlabs.org/comment/3678501/","msgid":"<0503f085-784f-40fd-842d-07c6b66373b3@linaro.org>","list_archive_url":null,"date":"2026-04-17T06:25:25","subject":"Re: [PATCH v3 15/17] hw/arm/aspeed_ast27x0: Set EHCI descriptor\n address offset","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 03:50, Jamin Lin wrote:\n> On AST2700 platforms, system DRAM is mapped above 4GB with the\n> base address at 0x400000000.\n> \n> The Linux EHCI driver programs the segment register to zero when\n> 64-bit addressing is supported. As a result, descriptor addresses\n> derived from the EHCI registers do not include the DRAM base\n> address.\n> \n> Descriptor memory is allocated through the DMA API with a 64-bit\n> DMA mask, which allows descriptors to be placed in DRAM above 4GB.\n> When running on AST2700, this means EHCI queue heads (QH) and queue\n> element transfer descriptors (qTD) reside at addresses starting\n> from 0x400000000.\n> \n> Set the descriptor-addr-offset property to the DRAM base so the\n> emulated EHCI controller can construct the correct descriptor\n> addresses when accessing system memory.\n> \n> Signed-off-by: Jamin Lin \n> ---\n> hw/arm/aspeed_ast27x0.c | 3 +++\n> 1 file changed, 3 insertions(+)\n> \n> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c\n> index 4a1f7cad73..3cdbf78ac1 100644\n> --- a/hw/arm/aspeed_ast27x0.c\n> +++ b/hw/arm/aspeed_ast27x0.c\n> @@ -858,6 +858,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n> for (i = 0; i < sc->ehcis_num; i++) {\n> object_property_set_bool(OBJECT(&s->ehci[i]), \"caps-64bit-addr\", true,\n> &error_abort);\n> + object_property_set_int(OBJECT(&s->ehci[i]), \"descriptor-addr-offset\",\n> + sc->memmap[ASPEED_DEV_SDRAM],\n> + &error_abort);\n\nSquash with previous? Or invert 14 <-> 15 order?","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=GZ4Eo7Y6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxlHy2MpFz1yDF\n\tfor ; Fri, 17 Apr 2026 16:25:50 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDce1-0000sY-Ar; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::329;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3680223,"web_url":"http://patchwork.ozlabs.org/comment/3680223/","msgid":"","list_archive_url":null,"date":"2026-04-22T05:03:37","subject":"RE: [PATCH v3 15/17] hw/arm/aspeed_ast27x0: Set EHCI descriptor\n address offset","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"content":"Hi Philippe\n\n> Subject: Re: [PATCH v3 15/17] hw/arm/aspeed_ast27x0: Set EHCI descriptor\n> address offset\n> \n> On 16/4/26 03:50, Jamin Lin wrote:\n> > On AST2700 platforms, system DRAM is mapped above 4GB with the base\n> > address at 0x400000000.\n> >\n> > The Linux EHCI driver programs the segment register to zero when\n> > 64-bit addressing is supported. As a result, descriptor addresses\n> > derived from the EHCI registers do not include the DRAM base address.\n> >\n> > Descriptor memory is allocated through the DMA API with a 64-bit DMA\n> > mask, which allows descriptors to be placed in DRAM above 4GB.\n> > When running on AST2700, this means EHCI queue heads (QH) and queue\n> > element transfer descriptors (qTD) reside at addresses starting from\n> > 0x400000000.\n> >\n> > Set the descriptor-addr-offset property to the DRAM base so the\n> > emulated EHCI controller can construct the correct descriptor\n> > addresses when accessing system memory.\n> >\n> > Signed-off-by: Jamin Lin \n> > ---\n> > hw/arm/aspeed_ast27x0.c | 3 +++\n> > 1 file changed, 3 insertions(+)\n> >\n> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index\n> > 4a1f7cad73..3cdbf78ac1 100644\n> > --- a/hw/arm/aspeed_ast27x0.c\n> > +++ b/hw/arm/aspeed_ast27x0.c\n> > @@ -858,6 +858,9 @@ static void aspeed_soc_ast2700_realize(DeviceState\n> *dev, Error **errp)\n> > for (i = 0; i < sc->ehcis_num; i++) {\n> > object_property_set_bool(OBJECT(&s->ehci[i]),\n> \"caps-64bit-addr\", true,\n> > &error_abort);\n> > + object_property_set_int(OBJECT(&s->ehci[i]),\n> \"descriptor-addr-offset\",\n> > +\n> sc->memmap[ASPEED_DEV_SDRAM],\n> > + &error_abort);\n> \n> Squash with previous? Or invert 14 <-> 15 order?\nThanks for the suggestion and review.\nWill invert patch order.\nJamin","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=SSmTIXd+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=aspeedtech.com;"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0nFM71Plz1yD5\n\tfor ; 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