[{"id":3678527,"web_url":"http://patchwork.ozlabs.org/comment/3678527/","msgid":"","list_archive_url":null,"date":"2026-04-17T07:16:02","subject":"RE: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC","submitter":{"id":4529,"url":"http://patchwork.ozlabs.org/api/people/4529/","name":"Tian, Kevin","email":"kevin.tian@intel.com"},"content":"> From: Ankit Agrawal \n> Sent: Thursday, April 16, 2026 9:45 AM\n> \n> +\n> +static int nvgrace_gpu_wait_device_ready_cxl(struct\n> nvgrace_gpu_pci_core_device *nvdev)\n> +{\n> +\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n> +\tint cxl_dvsec = nvdev->cxl_dvsec;\n> +\tunsigned long mem_info_valid_deadline;\n> +\tunsigned long timeout;\n> +\tu32 dvsec_memory_status;\n> +\tu8 mem_active_timeout;\n> +\n> +\tpci_read_config_dword(pdev, cxl_dvsec +\n> PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n> +\t\t\t &dvsec_memory_status);\n> +\n> +\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n> +\t\treturn 0;\n> +\n> +\tmem_active_timeout =\n> FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n> +\t\t\t\t dvsec_memory_status);\n\nSashiko pointed out that \" the Memory_Active_Timeout field is\nonly valid when the Memory_Info_Valid bit is set \". If it's true\nthen blindly reading it here is incorrect.\n\nhttps://sashiko.dev/#/patchset/20260416014504.63067-1-ankita%40nvidia.com\n\n> @@ -1146,11 +1218,16 @@ static bool\n> nvgrace_gpu_has_mig_hw_bug(struct pci_dev *pdev)\n> * Ensure that the BAR0 region is enabled before accessing the\n> * registers.\n> */\n> -static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n> +static int nvgrace_gpu_probe_check_device_ready(struct\n> nvgrace_gpu_pci_core_device *nvdev)\n\nthe comment above should be updated too.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=BeiDjVin;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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On probe and after reset, the\n> driver reads the CXL Device DVSEC capability to determine whether the\n> GPU memory is valid. This is checked by polling on the Memory_Active bit\n> based on the Memory_Active_Timeout. Also check if MEM_INFO_VALID is set\n> within 1 second per CXL spec 4.0 Tables 8-13. If not, return error.\n>\n> A static inline wrapper dispatches to the appropriate readiness check\n> based on whether the CXL DVSEC capability is present.\n>\n> Add PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout\n> field encoding.\n>\n> Signed-off-by: Ankit Agrawal \n\nTested-and-Acked-by: Nirmoy Das ","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=cSajlonD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52777-incoming=patchwork.ozlabs.org@vger.kernel.org;\n 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Apr 2026 13:20:56.4946\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 35e9238f-c145-43ef-8f45-08de9edfa7eb","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tMWH0EPF000C6195.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM4PR12MB5817"}},{"id":3679570,"web_url":"http://patchwork.ozlabs.org/comment/3679570/","msgid":"<202604210425.SVQZamM3-lkp@intel.com>","list_archive_url":null,"date":"2026-04-20T20:09:41","subject":"Re: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU\n readiness check via CXL DVSEC","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Ankit,\n\nkernel test robot noticed the following build errors:\n\n[auto build test ERROR on awilliam-vfio/next]\n[also build test ERROR on awilliam-vfio/for-linus pci/next pci/for-linus linus/master v7.0 next-20260420]\n[If your patch is applied to the wrong git tree, kindly drop us a note.\nAnd when submitting patch, we suggest to use '--base' as documented in\nhttps://git-scm.com/docs/git-format-patch#_base_tree_information]\n\nurl: https://github.com/intel-lab-lkp/linux/commits/Ankit-Agrawal/vfio-nvgrace-gpu-Add-Blackwell-Next-GPU-readiness-check-via-CXL-DVSEC/20260419-053131\nbase: https://github.com/awilliam/linux-vfio.git next\npatch link: https://lore.kernel.org/r/20260416014504.63067-1-ankita%40nvidia.com\npatch subject: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC\nconfig: s390-allmodconfig (https://download.01.org/0day-ci/archive/20260421/202604210425.SVQZamM3-lkp@intel.com/config)\ncompiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)\nreproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260421/202604210425.SVQZamM3-lkp@intel.com/reproduce)\n\nIf you fix the issue in a separate patch/commit (i.e. not just a new version of\nthe same patch/commit), kindly add following tags\n| Reported-by: kernel test robot \n| Closes: https://lore.kernel.org/oe-kbuild-all/202604210425.SVQZamM3-lkp@intel.com/\n\nAll errors (new ones prefixed by >>):\n\n>> drivers/vfio/pci/nvgrace-gpu/main.c:296:23: error: call to undeclared function 'FIELD_GET'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]\n 296 | mem_active_timeout = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n | ^\n 1 error generated.\n\n\nvim +/FIELD_GET +296 drivers/vfio/pci/nvgrace-gpu/main.c\n\n 280\t\n 281\tstatic int nvgrace_gpu_wait_device_ready_cxl(struct nvgrace_gpu_pci_core_device *nvdev)\n 282\t{\n 283\t\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n 284\t\tint cxl_dvsec = nvdev->cxl_dvsec;\n 285\t\tunsigned long mem_info_valid_deadline;\n 286\t\tunsigned long timeout;\n 287\t\tu32 dvsec_memory_status;\n 288\t\tu8 mem_active_timeout;\n 289\t\n 290\t\tpci_read_config_dword(pdev, cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n 291\t\t\t\t &dvsec_memory_status);\n 292\t\n 293\t\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n 294\t\t\treturn 0;\n 295\t\n > 296\t\tmem_active_timeout = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n 297\t\t\t\t\t dvsec_memory_status);\n 298\t\n 299\t\ttimeout = jiffies +\n 300\t\t\t msecs_to_jiffies(cxl_mem_active_timeout_ms(mem_active_timeout));\n 301\t\n 302\t\tmem_info_valid_deadline = jiffies + msecs_to_jiffies(POLL_QUANTUM_MS);\n 303\t\n 304\t\tdo {\n 305\t\t\tpci_read_config_dword(pdev,\n 306\t\t\t\t\t cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n 307\t\t\t\t\t &dvsec_memory_status);\n 308\t\n 309\t\t\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n 310\t\t\t\treturn 0;\n 311\t\n 312\t\t\t/* Bail early if MEM_INFO_VALID is not set within 1 second */\n 313\t\t\tif (!(dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n 314\t\t\t time_after(jiffies, mem_info_valid_deadline))\n 315\t\t\t\treturn -ETIME;\n 316\t\n 317\t\t\tmsleep(POLL_QUANTUM_MS);\n 318\t\t} while (!time_after(jiffies, timeout));\n 319\t\n 320\t\treturn -ETIME;\n 321\t}\n 322","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=DiAbU0Ac;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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d=\"scan'208\";a=\"88257774\"","E=Sophos;i=\"6.23,190,1770624000\";\n d=\"scan'208\";a=\"236793311\""],"X-ExtLoop1":"1","Date":"Tue, 21 Apr 2026 04:09:41 +0800","From":"kernel test robot ","To":"Ankit Agrawal , alex@shazbot.org,\n\tkvm@vger.kernel.org","Cc":"llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, jgg@ziepe.ca,\n\tyishaih@nvidia.com, skolothumtho@nvidia.com, kevin.tian@intel.com,\n\tankita@nvidia.com, bhelgaas@google.com,\n\tlinux-kernel@vger.kernel.org, linux-pci@vger.kernel.org","Subject":"Re: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU\n readiness check via CXL DVSEC","Message-ID":"<202604210425.SVQZamM3-lkp@intel.com>","References":"<20260416014504.63067-1-ankita@nvidia.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260416014504.63067-1-ankita@nvidia.com>"}},{"id":3679652,"web_url":"http://patchwork.ozlabs.org/comment/3679652/","msgid":"<202604211223.HLb8onLi-lkp@intel.com>","list_archive_url":null,"date":"2026-04-21T02:37:01","subject":"Re: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU\n readiness check via CXL DVSEC","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Ankit,\n\nkernel test robot noticed the following build errors:\n\n[auto build test ERROR on awilliam-vfio/next]\n[also build test ERROR on awilliam-vfio/for-linus pci/next pci/for-linus linus/master v7.0 next-20260420]\n[If your patch is applied to the wrong git tree, kindly drop us a note.\nAnd when submitting patch, we suggest to use '--base' as documented in\nhttps://git-scm.com/docs/git-format-patch#_base_tree_information]\n\nurl: https://github.com/intel-lab-lkp/linux/commits/Ankit-Agrawal/vfio-nvgrace-gpu-Add-Blackwell-Next-GPU-readiness-check-via-CXL-DVSEC/20260419-053131\nbase: https://github.com/awilliam/linux-vfio.git next\npatch link: https://lore.kernel.org/r/20260416014504.63067-1-ankita%40nvidia.com\npatch subject: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC\nconfig: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20260421/202604211223.HLb8onLi-lkp@intel.com/config)\ncompiler: alpha-linux-gcc (GCC) 15.2.0\nreproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260421/202604211223.HLb8onLi-lkp@intel.com/reproduce)\n\nIf you fix the issue in a separate patch/commit (i.e. not just a new version of\nthe same patch/commit), kindly add following tags\n| Reported-by: kernel test robot \n| Closes: https://lore.kernel.org/oe-kbuild-all/202604211223.HLb8onLi-lkp@intel.com/\n\nAll errors (new ones prefixed by >>):\n\n drivers/vfio/pci/nvgrace-gpu/main.c: In function 'nvgrace_gpu_wait_device_ready_cxl':\n>> drivers/vfio/pci/nvgrace-gpu/main.c:296:30: error: implicit declaration of function 'FIELD_GET' [-Wimplicit-function-declaration]\n 296 | mem_active_timeout = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n | ^~~~~~~~~\n\n\nvim +/FIELD_GET +296 drivers/vfio/pci/nvgrace-gpu/main.c\n\n 280\t\n 281\tstatic int nvgrace_gpu_wait_device_ready_cxl(struct nvgrace_gpu_pci_core_device *nvdev)\n 282\t{\n 283\t\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n 284\t\tint cxl_dvsec = nvdev->cxl_dvsec;\n 285\t\tunsigned long mem_info_valid_deadline;\n 286\t\tunsigned long timeout;\n 287\t\tu32 dvsec_memory_status;\n 288\t\tu8 mem_active_timeout;\n 289\t\n 290\t\tpci_read_config_dword(pdev, cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n 291\t\t\t\t &dvsec_memory_status);\n 292\t\n 293\t\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n 294\t\t\treturn 0;\n 295\t\n > 296\t\tmem_active_timeout = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n 297\t\t\t\t\t dvsec_memory_status);\n 298\t\n 299\t\ttimeout = jiffies +\n 300\t\t\t msecs_to_jiffies(cxl_mem_active_timeout_ms(mem_active_timeout));\n 301\t\n 302\t\tmem_info_valid_deadline = jiffies + msecs_to_jiffies(POLL_QUANTUM_MS);\n 303\t\n 304\t\tdo {\n 305\t\t\tpci_read_config_dword(pdev,\n 306\t\t\t\t\t cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n 307\t\t\t\t\t &dvsec_memory_status);\n 308\t\n 309\t\t\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n 310\t\t\t\treturn 0;\n 311\t\n 312\t\t\t/* Bail early if MEM_INFO_VALID is not set within 1 second */\n 313\t\t\tif (!(dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n 314\t\t\t time_after(jiffies, mem_info_valid_deadline))\n 315\t\t\t\treturn -ETIME;\n 316\t\n 317\t\t\tmsleep(POLL_QUANTUM_MS);\n 318\t\t} while (!time_after(jiffies, timeout));\n 319\t\n 320\t\treturn -ETIME;\n 321\t}\n 322","headers":{"Return-Path":"\n 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DVSEC","Message-ID":"<202604211223.HLb8onLi-lkp@intel.com>","References":"<20260416014504.63067-1-ankita@nvidia.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260416014504.63067-1-ankita@nvidia.com>"}}]