[{"id":3677875,"web_url":"http://patchwork.ozlabs.org/comment/3677875/","msgid":"<34374075-e340-4294-ae43-62d1422b5029@linaro.org>","list_archive_url":null,"date":"2026-04-16T00:13:37","subject":"Re: [RFC PATCH v5 4/6] target/mips: Convert MSA LD/ST.W (Word Vector)","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/16/26 06:20, Philippe Mathieu-Daudé wrote:\n> Replace runtime helpers by translation.\n> \n> Replace the legacy cpu_ld/st*_data_ra() calls by\n> tcg_gen_qemu_ld/st() which allow to respect atomicity.\n> \n> Signed-off-by: Philippe Mathieu-Daudé \n> ---\n> target/mips/tcg/msa_helper.h.inc | 1 -\n> target/mips/tcg/msa_helper.c | 47 --------------------------------\n> target/mips/tcg/msa_translate.c | 20 ++++++++++----\n> 3 files changed, 14 insertions(+), 54 deletions(-)\n\nModulo new temps for store,\n\nReviewed-by: Richard Henderson \n\n\nr~\n\n> \n> diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc\n> index 86a79bf804c..f0d31ceef29 100644\n> --- a/target/mips/tcg/msa_helper.h.inc\n> +++ b/target/mips/tcg/msa_helper.h.inc\n> @@ -436,6 +436,5 @@ DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)\n> #define MSALDST_PROTO(type) \\\n> DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \\\n> DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)\n> -MSALDST_PROTO(w)\n> MSALDST_PROTO(d)\n> #undef MSALDST_PROTO\n> diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c\n> index 5489d8830dd..c93c0cddebc 100644\n> --- a/target/mips/tcg/msa_helper.c\n> +++ b/target/mips/tcg/msa_helper.c\n> @@ -8212,32 +8212,6 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,\n> /* Element-by-element access macros */\n> #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))\n> \n> -static inline uint64_t bswap32x2(uint64_t x)\n> -{\n> - return ror64(bswap64(x), 32);\n> -}\n> -\n> -void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,\n> - target_ulong addr)\n> -{\n> - wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n> - uintptr_t ra = GETPC();\n> - uint64_t d0, d1;\n> -\n> - /*\n> - * Load 8 bytes at a time. Use little-endian load, then for\n> - * big-endian target, we must then bswap the two words.\n> - */\n> - d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);\n> - d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);\n> - if (mips_env_is_bigendian(env)) {\n> - d0 = bswap32x2(d0);\n> - d1 = bswap32x2(d1);\n> - }\n> - pwd->d[0] = d0;\n> - pwd->d[1] = d1;\n> -}\n> -\n> void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,\n> target_ulong addr)\n> {\n> @@ -8269,27 +8243,6 @@ static inline void ensure_writable_pages(CPUMIPSState *env,\n> }\n> }\n> \n> -void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,\n> - target_ulong addr)\n> -{\n> - wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n> - int mmu_idx = mips_env_mmu_index(env);\n> - uintptr_t ra = GETPC();\n> - uint64_t d0, d1;\n> -\n> - ensure_writable_pages(env, addr, mmu_idx, ra);\n> -\n> - /* Store 8 bytes at a time. See helper_msa_ld_w. */\n> - d0 = pwd->d[0];\n> - d1 = pwd->d[1];\n> - if (mips_env_is_bigendian(env)) {\n> - d0 = bswap32x2(d0);\n> - d1 = bswap32x2(d1);\n> - }\n> - cpu_stq_le_data_ra(env, addr + 0, d0, ra);\n> - cpu_stq_le_data_ra(env, addr + 8, d1, ra);\n> -}\n> -\n> void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,\n> target_ulong addr)\n> {\n> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\n> index 111d9eedd11..8486508f5ba 100644\n> --- a/target/mips/tcg/msa_translate.c\n> +++ b/target/mips/tcg/msa_translate.c\n> @@ -770,11 +770,21 @@ static void gen_bswap16x4_i64(TCGv_i64 dst, TCGv_i64 src)\n> tcg_gen_or_i64(dst, t0, t1); /* dst = badcfebg */\n> }\n> \n> +/*\n> + * Byte pattern: abcd.efgh -> dcba.hgfe\n> + */\n> +static void gen_bswap32x2_i64(TCGv_i64 dst, TCGv_i64 src)\n> +{\n> + tcg_gen_bswap64_i64(dst, src);\n> + tcg_gen_rotri_i64(dst, dst, 32);\n> +}\n> +\n> static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n> {\n> static const MemOp mo_atom_df[4] = {\n> MO_ATOM_NONE,\n> MO_ATOM_SUBALIGN, /* Slightly stronger than required */\n> + MO_ATOM_SUBALIGN, /* Slightly stronger than required */\n> };\n> TCGv_i32 wd;\n> TCGv_i128 t16;\n> @@ -795,18 +805,12 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n> \n> if (is_load) {\n> switch (a->df) {\n> - case 2:\n> - gen_helper_msa_ld_w(tcg_env, wd, addr);\n> - return true;\n> case 3:\n> gen_helper_msa_ld_d(tcg_env, wd, addr);\n> return true;\n> }\n> } else {\n> switch (a->df) {\n> - case 2:\n> - gen_helper_msa_st_w(tcg_env, wd, addr);\n> - return true;\n> case 3:\n> gen_helper_msa_st_d(tcg_env, wd, addr);\n> return true;\n> @@ -830,6 +834,10 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n> gen_bswap16x4_i64(d0, d0);\n> gen_bswap16x4_i64(d1, d1);\n> break;\n> + case 2:\n> + gen_bswap32x2_i64(d0, d0);\n> + gen_bswap32x2_i64(d1, d1);\n> + break;\n> }\n> }\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=tPtL2W6I;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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