[{"id":3677879,"web_url":"http://patchwork.ozlabs.org/comment/3677879/","msgid":"","list_archive_url":null,"date":"2026-04-16T00:18:47","subject":"Re: [RFC PATCH v5 6/6] target/mips: Endian-swap MSA LD/ST.D\n (Doubleword Vector)","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/16/26 06:20, Philippe Mathieu-Daudé wrote:\n> Doubleword Vector entries need to be swapped w.r.t. endianness.\n> \n> Fixes: 83be6b54123 (\"Fix MSA instructions LD. on big endian host\")\n> Fixes: 6decc572dce (\"Fix MSA instructions ST. on big endian host\")\n> Signed-off-by: Philippe Mathieu-Daudé \n> ---\n> Probably optimizable since tcg_gen_qemu_ld/st_i128 handles MO_BSWAP.\n> ---\n> target/mips/tcg/msa_translate.c | 4 ++++\n> 1 file changed, 4 insertions(+)\n> \n> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\n> index b1d764bd179..63d797a39b7 100644\n> --- a/target/mips/tcg/msa_translate.c\n> +++ b/target/mips/tcg/msa_translate.c\n> @@ -822,6 +822,10 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n> gen_bswap32x2_i64(d0, d0);\n> gen_bswap32x2_i64(d1, d1);\n> break;\n> + case 3:\n> + tcg_gen_bswap64_i64(d0, d0);\n> + tcg_gen_bswap64_i64(d1, d1);\n> + break;\n> }\n> }\n> \n\nNo, this is just a fix to patch 5.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=U6At3i5x;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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