[{"id":3677721,"web_url":"http://patchwork.ozlabs.org/comment/3677721/","msgid":"<20260415-reacquire-handstand-d1923af82c9d@spud>","list_archive_url":null,"date":"2026-04-15T15:09:49","subject":"Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","submitter":{"id":84372,"url":"http://patchwork.ozlabs.org/api/people/84372/","name":"Conor Dooley","email":"conor@kernel.org"},"content":"On Wed, Apr 15, 2026 at 05:50:20PM +0800, dongxuyang@eswincomputing.com wrote:\n> From: Xuyang Dong \n> \n> The DesignWare PWM includes separate reset signals dedicated to each clock\n> domain:\n> The presetn signal resets logic in pclk domain.\n> The timer_N_resetn signal resets logic in the timer_N_clk domain.\n> The resets are active-low.\n> \n> Signed-off-by: Xuyang Dong \n\nThis commit implies that your hardware differs from existing devices,\nI think you should add a device-specific compatible.\n\n> ---\n> .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++\n> 1 file changed, 3 insertions(+)\n> \n> diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> index 7523a89a1773..a8bbad0360f8 100644\n> --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> @@ -43,6 +43,9 @@ properties:\n> - const: bus\n> - const: timer\n> \n> + resets:\n> + maxItems: 2\n> +\n> snps,pwm-number:\n> $ref: /schemas/types.yaml#/definitions/uint32\n> description: The number of PWM channels configured for this instance\n> -- \n> 2.34.1\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=oh15y+Iq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"PLShwbF4Er3TfYyf\"","Content-Disposition":"inline","In-Reply-To":"<20260415095020.1597-1-dongxuyang@eswincomputing.com>"}},{"id":3677996,"web_url":"http://patchwork.ozlabs.org/comment/3677996/","msgid":"<20260416-wandering-solemn-uakari-083ae7@quoll>","list_archive_url":null,"date":"2026-04-16T08:24:29","subject":"Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Wed, Apr 15, 2026 at 04:09:49PM +0100, Conor Dooley wrote:\n> On Wed, Apr 15, 2026 at 05:50:20PM +0800, dongxuyang@eswincomputing.com wrote:\n> > From: Xuyang Dong \n> > \n> > The DesignWare PWM includes separate reset signals dedicated to each clock\n> > domain:\n> > The presetn signal resets logic in pclk domain.\n> > The timer_N_resetn signal resets logic in the timer_N_clk domain.\n> > The resets are active-low.\n> > \n> > Signed-off-by: Xuyang Dong \n> \n> This commit implies that your hardware differs from existing devices,\n> I think you should add a device-specific compatible.\n> \n> > ---\n> > .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++\n> > 1 file changed, 3 insertions(+)\n> > \n> > diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > index 7523a89a1773..a8bbad0360f8 100644\n> > --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > @@ -43,6 +43,9 @@ properties:\n> > - const: bus\n> > - const: timer\n> > \n> > + resets:\n> > + maxItems: 2\n\nAnd this should really be listed with description, because order is\nfixed.\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=YbNL1BW3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<20260415-reacquire-handstand-d1923af82c9d@spud>"}},{"id":3678062,"web_url":"http://patchwork.ozlabs.org/comment/3678062/","msgid":"<281f7aa3.5575.19d95a879f8.Coremail.dongxuyang@eswincomputing.com>","list_archive_url":null,"date":"2026-04-16T09:38:59","subject":"Re: Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","submitter":{"id":90849,"url":"http://patchwork.ozlabs.org/api/people/90849/","name":"Xuyang Dong","email":"dongxuyang@eswincomputing.com"},"content":"> > > \n> > > The DesignWare PWM includes separate reset signals dedicated to each clock\n> > > domain:\n> > > The presetn signal resets logic in pclk domain.\n> > > The timer_N_resetn signal resets logic in the timer_N_clk domain.\n> > > The resets are active-low.\n> > > \n> > > Signed-off-by: Xuyang Dong \n> > \n> > This commit implies that your hardware differs from existing devices,\n> > I think you should add a device-specific compatible.\n> > \n\nHi Conor and Krzysztof,\n\nThe DesignWare PWM Databook for 2.13a says: \"The DW_apb_timers includes \nseparate reset signals dedicated to each clock domain\". They are:\nThe presetn signal resets logic in pclk domain (i.e., the bus clock in DT).\nThe timer_N_resetn signal resets logic in the timer_N_clk domain (i.e.,\nthe timer clock in DT).\n\nThese reset signals are optional; it is up to the designer's \nimplementation.\n\nAccording to [1], the applied YAML is also based on 2.13a, so our \nhardware is the same as the existing devices. It's just that these two \nreset signals were missing from the original YAML binding.\n\n[1] https://lore.kernel.org/linux-pwm/8bb5103d-803e-90d2-fd93-132bb2aac2d6@sifive.com/\n\n> > > ---\n> > > .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++\n> > > 1 file changed, 3 insertions(+)\n> > > \n> > > diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > index 7523a89a1773..a8bbad0360f8 100644\n> > > --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > @@ -43,6 +43,9 @@ properties:\n> > > - const: bus\n> > > - const: timer\n> > > \n> > > + resets:\n> > > + maxItems: 2\n> \n> And this should really be listed with description, because order is\n> fixed.\n> \n\nThe description of resets will be listed in next version.\n\nBest regards,\nXuyang Dong","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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Thu, 16 Apr 2026 17:38:59 +0800 (GMT+08:00)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776332370; cv=none;\n b=SnnPILzjCyBoa7IZtM7GlAJzkXzlqjtqvzVrg6U95Ps6osUFzZ6f9MKTDKCMjCblufA6NSecy9WvrL7G9Cyt2TsQ+PO4M4QjcU+h3Vw3qDHmQRixA8VfKRtPJHeeG5q7uP92q2AspOY1Ji3+VxSkdJAhglTELumxE2nZvq5mZCM=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776332370; c=relaxed/simple;\n\tbh=T7CoLB2p6sG/di7D5Nmfq3bgVGiqmIyvmGldLZWNe50=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:References:Content-Type:\n\t MIME-Version:Message-ID;\n b=M9qq3iM5dkIMjQokcsHcEpoh4ewjmu7eQeYwVhh4nHJ7WfRMb6bO+8CX5VPY0QIpiZLM1YNgWxfzMH6eu5mp0K1NGbVPZyp41gAz3y/6Vf87m8fIapfYt4XDoPcpBWfozIdc/c5ODdWxzU0rzW+Xnr5g+7MMqVhkHQ6XBkdtmtw=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=eswincomputing.com;\n spf=pass smtp.mailfrom=eswincomputing.com;\n arc=none smtp.client-ip=162.243.161.220","Date":"Thu, 16 Apr 2026 17:38:59 +0800 (GMT+08:00)","X-CM-HeaderCharset":"UTF-8","From":"\"Xuyang Dong\" ","To":"\"Krzysztof Kozlowski\" ,\n\t\"Conor Dooley\" ","Cc":"ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org,\n\tconor+dt@kernel.org, ben-linux@fluff.org, ben.dooks@codethink.co.uk,\n\tp.zabel@pengutronix.de, linux-pwm@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tningyu@eswincomputing.com, linmin@eswincomputing.com,\n\txuxiang@eswincomputing.com, wangguosheng@eswincomputing.com,\n\tpinkesh.vaghela@einfochips.com","Subject":"Re: Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","X-Priority":"3","X-Mailer":"Coremail Webmail Server Version 2024.2-cmXT6 build\n 20241203(6b039d88) Copyright (c) 2002-2026 www.mailtech.cn\n mispb-72143050-eaf5-4703-89e0-86624513b4ce-eswincomputing.com","In-Reply-To":"<20260416-wandering-solemn-uakari-083ae7@quoll>","References":"<20260415094908.1539-1-dongxuyang@eswincomputing.com>\n <20260415095020.1597-1-dongxuyang@eswincomputing.com>\n <20260415-reacquire-handstand-d1923af82c9d@spud>\n <20260416-wandering-solemn-uakari-083ae7@quoll>","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=UTF-8","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Message-ID":"<281f7aa3.5575.19d95a879f8.Coremail.dongxuyang@eswincomputing.com>","X-Coremail-Locale":"zh_CN","X-CM-TRANSID":"TQJkCgA3TJ8zruBp7yYSAA--.2351W","X-CM-SenderInfo":"pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/1tbiAgETAmnfvg1VQ\n\tQAAsD","X-Coremail-Antispam":"1Ur529EdanIXcx71UUUUU7IcSsGvfJ3iIAIbVAYjsxI4VWxJw\n\tCS07vEb4IE77IF4wCS07vE1I0E4x80FVAKz4kxMIAIbVAFxVCaYxvI4VCIwcAKzIAtYxBI\n\tdaVFxhVjvjDU="}},{"id":3678255,"web_url":"http://patchwork.ozlabs.org/comment/3678255/","msgid":"<20260416-flashcard-shadily-a0ddd2f12ff8@spud>","list_archive_url":null,"date":"2026-04-16T15:29:29","subject":"Re: Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","submitter":{"id":84372,"url":"http://patchwork.ozlabs.org/api/people/84372/","name":"Conor Dooley","email":"conor@kernel.org"},"content":"On Thu, Apr 16, 2026 at 05:38:59PM +0800, Xuyang Dong wrote:\n> > > > \n> > > > The DesignWare PWM includes separate reset signals dedicated to each clock\n> > > > domain:\n> > > > The presetn signal resets logic in pclk domain.\n> > > > The timer_N_resetn signal resets logic in the timer_N_clk domain.\n> > > > The resets are active-low.\n> > > > \n> > > > Signed-off-by: Xuyang Dong \n> > > \n> > > This commit implies that your hardware differs from existing devices,\n> > > I think you should add a device-specific compatible.\n> > > \n> \n> Hi Conor and Krzysztof,\n> \n> The DesignWare PWM Databook for 2.13a says: \"The DW_apb_timers includes \n> separate reset signals dedicated to each clock domain\". They are:\n> The presetn signal resets logic in pclk domain (i.e., the bus clock in DT).\n> The timer_N_resetn signal resets logic in the timer_N_clk domain (i.e.,\n> the timer clock in DT).\n> \n> These reset signals are optional; it is up to the designer's \n> implementation.\n\nRight, and it's that \"designer's implementation\" that warrants a\ndevice-specific compatible.\n\n> \n> According to [1], the applied YAML is also based on 2.13a, so our \n> hardware is the same as the existing devices. It's just that these two \n> reset signals were missing from the original YAML binding.\n> \n> [1] https://lore.kernel.org/linux-pwm/8bb5103d-803e-90d2-fd93-132bb2aac2d6@sifive.com/\n> \n> > > > ---\n> > > > .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++\n> > > > 1 file changed, 3 insertions(+)\n> > > > \n> > > > diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > > index 7523a89a1773..a8bbad0360f8 100644\n> > > > --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > > +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > > @@ -43,6 +43,9 @@ properties:\n> > > > - const: bus\n> > > > - const: timer\n> > > > \n> > > > + resets:\n> > > > + maxItems: 2\n> > \n> > And this should really be listed with description, because order is\n> > fixed.\n> > \n> \n> The description of resets will be listed in next version.\n> \n> Best regards,\n> Xuyang Dong","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Wxe8kejo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"RT0aWT33ZuoPw3Hs\"","Content-Disposition":"inline","In-Reply-To":"\n <281f7aa3.5575.19d95a879f8.Coremail.dongxuyang@eswincomputing.com>"}},{"id":3678359,"web_url":"http://patchwork.ozlabs.org/comment/3678359/","msgid":"","list_archive_url":null,"date":"2026-04-16T19:53:56","subject":"Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","submitter":{"id":88416,"url":"http://patchwork.ozlabs.org/api/people/88416/","name":"Uwe Kleine-König","email":"ukleinek@kernel.org"},"content":"Hello,\n\nI suggest\n\n\tdt-bindings: pwm: dwc: Add optional reset\n\nas shortlog.\n\nBest regards\nUwe","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=cDb2lX/u;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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micalg=pgp-sha512;\n\tprotocol=\"application/pgp-signature\"; boundary=\"2u45m4lertypw5tb\"","Content-Disposition":"inline","In-Reply-To":"<20260415095020.1597-1-dongxuyang@eswincomputing.com>"}},{"id":3678462,"web_url":"http://patchwork.ozlabs.org/comment/3678462/","msgid":"<3b2e80d5.55a5.19d996c6821.Coremail.dongxuyang@eswincomputing.com>","list_archive_url":null,"date":"2026-04-17T03:11:51","subject":"Re: Re: Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset\n optional","submitter":{"id":90849,"url":"http://patchwork.ozlabs.org/api/people/90849/","name":"Xuyang Dong","email":"dongxuyang@eswincomputing.com"},"content":"> > > > > \n> > > > > The DesignWare PWM includes separate reset signals dedicated to each clock\n> > > > > domain:\n> > > > > The presetn signal resets logic in pclk domain.\n> > > > > The timer_N_resetn signal resets logic in the timer_N_clk domain.\n> > > > > The resets are active-low.\n> > > > > \n> > > > > Signed-off-by: Xuyang Dong \n> > > > \n> > > > This commit implies that your hardware differs from existing devices,\n> > > > I think you should add a device-specific compatible.\n> > > > \n> > \n> > Hi Conor and Krzysztof,\n> > \n> > The DesignWare PWM Databook for 2.13a says: \"The DW_apb_timers includes \n> > separate reset signals dedicated to each clock domain\". They are:\n> > The presetn signal resets logic in pclk domain (i.e., the bus clock in DT).\n> > The timer_N_resetn signal resets logic in the timer_N_clk domain (i.e.,\n> > the timer clock in DT).\n> > \n> > These reset signals are optional; it is up to the designer's \n> > implementation.\n> \n> Right, and it's that \"designer's implementation\" that warrants a\n> device-specific compatible.\n> \n\nHi Conor,\n\nThe YAML update for the new device-specific compatible is as follows:\n\nproperties:\n compatible:\n oneOf:\n - const: snps,dw-apb-timers-pwm2\n - items:\n - enum:\n - snps,dw-apb-timers-pwm-2.13a\n - const: snps,dw-apb-timers-pwm2\n\n reg:\n maxItems: 1\n\n \"#pwm-cells\":\n const: 3\n\n clocks:\n items:\n - description: Interface bus clock\n - description: PWM reference clock\n\n clock-names:\n items:\n - const: bus\n - const: timer\n\n resets:\n items:\n - description: Interface bus reset\n - description: PWM timer logic reset\n\n snps,pwm-number:\n $ref: /schemas/types.yaml#/definitions/uint32\n description: The number of PWM channels configured for this instance\n enum: [1, 2, 3, 4, 5, 6, 7, 8]\n\nrequired:\n - compatible\n - reg\n - clocks\n - clock-names\n\nallOf:\n - $ref: pwm.yaml#\n\n - if:\n properties:\n compatible:\n contains:\n const: snps,dw-apb-timers-pwm-2.13a\n\n then:\n required:\n - resets\n\nIn your opinion, is this modification accurate?\n\nBest regards,\nXuyang Dong\n\n> > \n> > According to [1], the applied YAML is also based on 2.13a, so our \n> > hardware is the same as the existing devices. It's just that these two \n> > reset signals were missing from the original YAML binding.\n> > \n> > [1] https://lore.kernel.org/linux-pwm/8bb5103d-803e-90d2-fd93-132bb2aac2d6@sifive.com/\n> > \n> > > > > ---\n> > > > > .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++\n> > > > > 1 file changed, 3 insertions(+)\n> > > > > \n> > > > > diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > > > index 7523a89a1773..a8bbad0360f8 100644\n> > > > > --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > > > +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n> > > > > @@ -43,6 +43,9 @@ properties:\n> > > > > - const: bus\n> > > > > - const: timer\n> > > > > \n> > > > > + resets:\n> > > > > + maxItems: 2\n> > > \n> > > And this should really be listed with description, because order is\n> > > fixed.\n> > > \n> > \n> > The description of resets will be listed in next version.\n> > \n> > Best regards,\n> > Xuyang Dong","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Fri, 17 Apr 2026 11:11:51 +0800 (GMT+08:00)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776395543; cv=none;\n b=h/QtHG/CW1VsHYW9wqaAhe7qttY5Y3hwdTWMAKza8yvkDxmxIvvTfEXMiTpWDEBVnPE8wnCwDPmPnGz+A/51k5NNYNBIvrpvKv7ssr/eI3CqSPOyi2cA4iigsZwdiz/BeVXUdcp4L1obAjZOrw9iP9r1psIeHwZGiT1GChfc1dE=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776395543; c=relaxed/simple;\n\tbh=kqBVNGwxpKB1stgn4t21+OlgFdmZqmq8qQ6qKFQWzNY=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:References:Content-Type:\n\t MIME-Version:Message-ID;\n b=tz53W+ER2jWS8OnPzCLipwYbKAy3FToqGTZXDdXE7DNs3toBOFxIlBk54N+a+r5iaq8CTEiz6ipmvE7hizwFHQNv6agEleV78PgBvw/RQwfkEFrjljS3lYxBH91qU4R7LfkWoTvzfEc17Q3+kY/4cH3D+eQ8Q9i9xKjNeczjFfg=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=eswincomputing.com;\n spf=pass smtp.mailfrom=eswincomputing.com;\n arc=none smtp.client-ip=4.193.249.245","Date":"Fri, 17 Apr 2026 11:11:51 +0800 (GMT+08:00)","X-CM-HeaderCharset":"UTF-8","From":"\"Xuyang Dong\" ","To":"\"Conor Dooley\" ","Cc":"\"Krzysztof Kozlowski\" , ukleinek@kernel.org,\n\trobh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,\n\tben-linux@fluff.org, ben.dooks@codethink.co.uk,\n\tp.zabel@pengutronix.de, linux-pwm@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tningyu@eswincomputing.com, linmin@eswincomputing.com,\n\txuxiang@eswincomputing.com, wangguosheng@eswincomputing.com,\n\tpinkesh.vaghela@einfochips.com","Subject":"Re: Re: Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset\n optional","X-Priority":"3","X-Mailer":"Coremail Webmail Server Version 2024.2-cmXT6 build\n 20241203(6b039d88) Copyright (c) 2002-2026 www.mailtech.cn\n mispb-72143050-eaf5-4703-89e0-86624513b4ce-eswincomputing.com","In-Reply-To":"<20260416-flashcard-shadily-a0ddd2f12ff8@spud>","References":"<20260415094908.1539-1-dongxuyang@eswincomputing.com>\n <20260415095020.1597-1-dongxuyang@eswincomputing.com>\n <20260415-reacquire-handstand-d1923af82c9d@spud>\n <20260416-wandering-solemn-uakari-083ae7@quoll>\n <281f7aa3.5575.19d95a879f8.Coremail.dongxuyang@eswincomputing.com>\n <20260416-flashcard-shadily-a0ddd2f12ff8@spud>","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=UTF-8","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Message-ID":"<3b2e80d5.55a5.19d996c6821.Coremail.dongxuyang@eswincomputing.com>","X-Coremail-Locale":"zh_CN","X-CM-TRANSID":"TQJkCgA3TJ_3pOFp21YSAA--.2378W","X-CM-SenderInfo":"pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/1tbiAgEAAmnhD40Rb\n\tQAAs3","X-Coremail-Antispam":"1Ur529EdanIXcx71UUUUU7IcSsGvfJ3iIAIbVAYjsxI4VWxJw\n\tCS07vEb4IE77IF4wCS07vE1I0E4x80FVAKz4kxMIAIbVAFxVCaYxvI4VCIwcAKzIAtYxBI\n\tdaVFxhVjvjDU="}},{"id":3678464,"web_url":"http://patchwork.ozlabs.org/comment/3678464/","msgid":"<65568985.55a7.19d996e40c9.Coremail.dongxuyang@eswincomputing.com>","list_archive_url":null,"date":"2026-04-17T03:13:52","subject":"Re: Re: [PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","submitter":{"id":90849,"url":"http://patchwork.ozlabs.org/api/people/90849/","name":"Xuyang Dong","email":"dongxuyang@eswincomputing.com"},"content":"> \n> Hello,\n> \n> I suggest\n> \n> \tdt-bindings: pwm: dwc: Add optional reset\n> \n> as shortlog.\n> \n\nHi Uwe,\n\nThanks, I'll address this in the next version.\n\nBest regards,\nXuyang Dong","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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