[{"id":3677558,"web_url":"http://patchwork.ozlabs.org/comment/3677558/","msgid":"<177624504894.3320247.14684447771089927124.robh@kernel.org>","list_archive_url":null,"date":"2026-04-15T09:24:08","subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu\n resource","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Wed, 15 Apr 2026 10:01:53 +0200, Florian Eckert wrote:\n> The 'atu' information is already set in the dwc core, if it is specified\n> in the devicetree. The driver uses its own default, if not set in the\n> devicetree. This information is hardware specific and should therefore be\n> maintained in the devicetree rather than in the source.\n> \n> To be backward compatible, this field is not mandatory. If 'atu'\n> resource is not specified in the devicetree, the driver’s default value\n> is used.\n> \n> Signed-off-by: Florian Eckert \n> ---\n> Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 8 ++++++--\n> 1 file changed, 6 insertions(+), 2 deletions(-)\n> \n\nMy bot found errors running 'make dt_binding_check' on your patch:\n\nyamllint warnings/errors:\n\ndtschema/dtc warnings/errors:\nLexical error: Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dts:28.30-36 Unexpected 'config'\nError: Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dts:28.30-36 syntax error\nFATAL ERROR: Unable to parse input tree\nmake[2]: *** [scripts/Makefile.dtbs:140: Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dtb] Error 1\nmake[2]: *** Waiting for unfinished jobs....\nmake[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1601: dt_binding_check] Error 2\nmake: *** [Makefile:248: __sub-make] Error 2\n\ndoc reference errors (make refcheckdocs):\n\nSee https://patchwork.kernel.org/project/devicetree/patch/20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de\n\nThe base for the series is generally the latest rc1. A different dependency\nshould be noted in *this* patch.\n\nIf you already ran 'make dt_binding_check' and didn't see the above\nerror(s), then make sure 'yamllint' is installed and dt-schema is up to\ndate:\n\npip3 install dtschema --upgrade\n\nPlease check and re-submit after running the above command yourself. Note\nthat DT_SCHEMA_FILES can be set to your schema file to speed up checking\nyour schema. However, it must be unset to test all examples with your schema.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=JypY5ms0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52550-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"JypY5ms0\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwbWy5qMxz1yDF\n\tfor ; Wed, 15 Apr 2026 19:32:14 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 0B9B63009FBF\n\tfor ; Wed, 15 Apr 2026 09:24:13 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id EC28B333429;\n\tWed, 15 Apr 2026 09:24:11 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id C71F532D0CF;\n\tWed, 15 Apr 2026 09:24:11 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 2FB9CC19424;\n\tWed, 15 Apr 2026 09:24:11 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776245051; cv=none;\n b=KlKhD7xZzaYPYYpe6ddbwhnlKO7wFz/0vXB2+FNTgOhI3jJt7EMgFCrEL87Nyh4eEG7xBUX0aY6+2UQnKUQd4zjgRWoZULwMjw5gvlrEq60yGROPnt7FdwNwBVQU2hW0Lstxu+u6+9kyAddD5SUDQgb3o/2XWk+9t68gOypfwrE=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776245051; c=relaxed/simple;\n\tbh=wsSRf+FgtSM4Tmbmls0rwxi6ii/1NE9W0IbBIkaPRi0=;\n\th=Date:Content-Type:MIME-Version:From:Cc:To:In-Reply-To:References:\n\t Message-Id:Subject;\n b=eXP++HTpUQyQ9NBb/SUvKN+bzgT0rtl+Y/as50+XFIe1foo5syxB1DULaGeAIIDffnnjkPFFhfiLI5hGxvexVPTWOabCSjL+U+Yiewv3oem66CUwvuF4pvqKVLcE/5l8iOwCVUu0T1rUVdQb/AOlnqYgmiNyA3ZmM0pj3sxMRUA=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=JypY5ms0; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1776245051;\n\tbh=wsSRf+FgtSM4Tmbmls0rwxi6ii/1NE9W0IbBIkaPRi0=;\n\th=Date:From:Cc:To:In-Reply-To:References:Subject:From;\n\tb=JypY5ms0Oq9lbJcBPtM6l1MYZ3oGXeytjMCYXkAPu9kQAfw9pNXar0uj6kMjdm/Xo\n\t 1dCOmw8/X3BYlIt7+BcJDgQ/6FQrzXOclf0JP1e0yIO9WZ3BDe8RgxsQ2dCR+aQVey\n\t 8rsXyqOkhf1/J37L28oS9EDouk/94Hv3VVfiBAU9hLW94ETfL4Phu2uhQ3ndL4BXdh\n\t PaFZp5OYGqsubwy+rYV4z+WurFS7AMW897ygRtPL4cu8BaZWCDfWJWtXnm8BWa+Hr4\n\t jNCrW/0HEtl/onZGcftqqtIq8USkacoumHdLvP9/MYb8pv5P/n/F4Z0C0N+FC72KOL\n\t ZUo4FuWvGFX2A==","Date":"Wed, 15 Apr 2026 04:24:08 -0500","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"8bit","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","From":"\"Rob Herring (Arm)\" ","Cc":"Krzysztof Kozlowski , Eckert.Florian@googlemail.com,\n ms@dev.tdt.de, Bjorn Helgaas ,\n Manivannan Sadhasivam , Conor Dooley ,\n Johan Hovold , linux-kernel@vger.kernel.org,\n devicetree@vger.kernel.org, Ajay Agarwal ,\n Sajid Dalvi , linux-pci@vger.kernel.org, =?utf-8?q?Krzy?=\n\t=?utf-8?q?sztof_Wilczy=C5=84ski?= ,\n Lorenzo Pieralisi ","To":"Florian Eckert ","In-Reply-To":"<20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de>","References":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>\n <20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de>","Message-Id":"<177624504894.3320247.14684447771089927124.robh@kernel.org>","Subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu\n resource"}},{"id":3677626,"web_url":"http://patchwork.ozlabs.org/comment/3677626/","msgid":"","list_archive_url":null,"date":"2026-04-15T12:09:42","subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu resource","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Wed, Apr 15, 2026 at 3:02 AM Florian Eckert wrote:\n>\n> The 'atu' information is already set in the dwc core, if it is specified\n> in the devicetree. The driver uses its own default, if not set in the\n> devicetree. This information is hardware specific and should therefore be\n> maintained in the devicetree rather than in the source.\n>\n> To be backward compatible, this field is not mandatory. If 'atu'\n> resource is not specified in the devicetree, the driver’s default value\n> is used.\n>\n> Signed-off-by: Florian Eckert \n> ---\n> Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 8 ++++++--\n> 1 file changed, 6 insertions(+), 2 deletions(-)\n>\n> diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n> index 54e2890ae6314ac6847fc23f49440d05d66d87d4..9b7a8ef77585677841c7064c5001110bc2b65db1 100644\n> --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n> +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n> @@ -27,16 +27,19 @@ properties:\n> - const: snps,dw-pcie\n>\n> reg:\n> + minItems: 3\n> items:\n> - description: Controller control and status registers.\n> - description: PCIe configuration registers.\n> - description: Controller application registers.\n> + - description: Internal Address Translation Unit (iATU) registers.\n>\n> reg-names:\n\nDon't you need minItems here?\n\n> items:\n> - const: dbi\n> - const: config\n> - const: app\n> + - const: atu\n>\n> ranges:\n> maxItems: 1\n> @@ -95,8 +98,9 @@ examples:\n> #size-cells = <2>;\n> reg = <0xd0e00000 0x1000>,\n> <0xd2000000 0x800000>,\n> - <0xd0a41000 0x1000>;\n> - reg-names = \"dbi\", \"config\", \"app\";\n> + <0xd0a41000 0x1000>,\n> + <0xd0ec0000 0x1000>;\n> + reg-names = \"dbi\", config\", \"app\", \"atu\";\n> linux,pci-domain = <0>;\n> max-link-speed = <4>;\n> bus-range = <0x00 0x08>;\n>\n> --\n> 2.47.3\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=oZYEQIbg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52551-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"oZYEQIbg\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwg2133fHz1yCv\n\tfor ; Wed, 15 Apr 2026 22:10:01 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 73C3F3016ECC\n\tfor ; Wed, 15 Apr 2026 12:09:58 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 05B14343216;\n\tWed, 15 Apr 2026 12:09:57 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id D6D183382CB\n\tfor ; Wed, 15 Apr 2026 12:09:56 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 95572C4AF09\n\tfor ; Wed, 15 Apr 2026 12:09:56 +0000 (UTC)","by mail-ed1-f47.google.com with SMTP id\n 4fb4d7f45d1cf-671fe205535so2573256a12.2\n for ; Wed, 15 Apr 2026 05:09:56 -0700 (PDT)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776254996; cv=none;\n b=Q9rGJYxfciuXrbWtcHMi7AXmJWesMYDTAfzpKNg0R27bxCyD9N+1reP81JH4L6BDVRihxqi60rhIGHWmTqEY2cV1xjEEF8c5HS9K059xUEwomTzArwtU02bcgjrDAQLQcGWmfsIPflnXjB0laR8YmbTSG4kiCqV5kNkXXkvnWP0=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776254996; c=relaxed/simple;\n\tbh=IsZjVVDU7pDTf9EQdpLWQT5bHICKqDwTS3CU10zyGhY=;\n\th=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:\n\t To:Cc:Content-Type;\n b=ckn/khqMT7w09jR+DGSDN4V05DlvmrQaqZnieU0VA5hMdRb7gKJykBUSZrBx5vVu1bx7bChMzGR6W6UCw53fWN3wCGEOguph0ZWDcP+yLli2MieisfpBZjcEkPBkM7hnNcyrr+E0T9iMs4SyBL2F3J3sT72vOc+cawvHPWUGlQc=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=oZYEQIbg; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1776254996;\n\tbh=IsZjVVDU7pDTf9EQdpLWQT5bHICKqDwTS3CU10zyGhY=;\n\th=References:In-Reply-To:From:Date:Subject:To:Cc:From;\n\tb=oZYEQIbgYgB0OAggPowebovAj9VVCPvt8g3D0lWYRnkhRRb2ROQDa3eIczRO2Gykh\n\t KjpDYVDduOB0ByOCM+a5ykALNN42KrFfJQ+56KSijvxICBD0siV9vz5laEVeZu+zAA\n\t HCxmrqRdeAAB6/+EiCS18G/tVdPzvD5+b2aQOZZ3kV8pfH4enftLOmqj1gl1y19L6K\n\t wy7FTZ6h/MwN0GZ5zS5T831MdhnGn3qANjXmfHz2LikYsRpsgauVHLzPdmnmr3VKz9\n\t yvZD+8uiDyWstMXZzm8PCL2CCls8cPOarIvV7fvgtGVhgwqdcNabEvnlBlP5alYqA2\n\t Ed3VsbAc5ouow==","X-Forwarded-Encrypted":"i=1;\n AFNElJ951NGKrkK2AujSNnwg0AIypRGdzyw28fFeYHGCGJPCLOy4Vl8TupsFGh8ZzPYmUW61IqOG5gq9xhA=@vger.kernel.org","X-Gm-Message-State":"AOJu0YwiG+4I8vzuNpa6Iw1iU88m3IQC3XWW6yFWP8xBsEwTDh4JZaqN\n\tgjcv6MmlFspn26u645GxnuiA/BCaXtOnKArwL/3dsIGZvABwYj9v2jxVIY9R8LGbjPruKh4r2y3\n\t0WObMxTnrPhdVkFeMGqR1094lte+LNg==","X-Received":"by 2002:a05:6402:358c:b0:671:4565:6ee1 with SMTP id\n 4fb4d7f45d1cf-67145657271mr7292515a12.23.1776254995084; Wed, 15 Apr 2026\n 05:09:55 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>\n <20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de>","In-Reply-To":"<20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de>","From":"Rob Herring ","Date":"Wed, 15 Apr 2026 07:09:42 -0500","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AQROBzC_mAVp6zOHeu_bjQpvZzAb9oxCTbS_Ekqoq7x32sgUj1cFvFnCWugBd6I","Message-ID":"\n ","Subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu resource","To":"Florian Eckert ","Cc":"Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam ,\n Bjorn Helgaas , Johan Hovold ,\n Sajid Dalvi , Ajay Agarwal ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Eckert.Florian@googlemail.com, ms@dev.tdt.de","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3677633,"web_url":"http://patchwork.ozlabs.org/comment/3677633/","msgid":"","list_archive_url":null,"date":"2026-04-15T12:26:08","subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu\n resource","submitter":{"id":72238,"url":"http://patchwork.ozlabs.org/api/people/72238/","name":"Florian Eckert","email":"fe@dev.tdt.de"},"content":"On 2026-04-15 14:09, Rob Herring wrote:\n> On Wed, Apr 15, 2026 at 3:02 AM Florian Eckert wrote:\n>> \n>> The 'atu' information is already set in the dwc core, if it is \n>> specified\n>> in the devicetree. The driver uses its own default, if not set in the\n>> devicetree. This information is hardware specific and should therefore \n>> be\n>> maintained in the devicetree rather than in the source.\n>> \n>> To be backward compatible, this field is not mandatory. If 'atu'\n>> resource is not specified in the devicetree, the driver’s default \n>> value\n>> is used.\n>> \n>> Signed-off-by: Florian Eckert \n>> ---\n>> Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 8 ++++++--\n>> 1 file changed, 6 insertions(+), 2 deletions(-)\n>> \n>> diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml \n>> b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n>> index \n>> 54e2890ae6314ac6847fc23f49440d05d66d87d4..9b7a8ef77585677841c7064c5001110bc2b65db1 \n>> 100644\n>> --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n>> +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n>> @@ -27,16 +27,19 @@ properties:\n>> - const: snps,dw-pcie\n>> \n>> reg:\n>> + minItems: 3\n>> items:\n>> - description: Controller control and status registers.\n>> - description: PCIe configuration registers.\n>> - description: Controller application registers.\n>> + - description: Internal Address Translation Unit (iATU) \n>> registers.\n>> \n>> reg-names:\n> \n> Don't you need minItems here?\n\nYou're absolutely right, of course!\nMy fault. Thanks for pointing that out.\nI will wait 24 hours to send a v5 with this change.\n\nJust to clarify. How does the creator of DTS know which items are \nrequired.\nDoes that mean, in this case, that the last item is always optional and \nthe\nothers are absolutely essential?\n\n> \n>> items:\n>> - const: dbi\n>> - const: config\n>> - const: app\n>> + - const: atu\n>> \n>> ranges:\n>> maxItems: 1\n>> @@ -95,8 +98,9 @@ examples:\n>> #size-cells = <2>;\n>> reg = <0xd0e00000 0x1000>,\n>> <0xd2000000 0x800000>,\n>> - <0xd0a41000 0x1000>;\n>> - reg-names = \"dbi\", \"config\", \"app\";\n>> + <0xd0a41000 0x1000>,\n>> + <0xd0ec0000 0x1000>;\n>> + reg-names = \"dbi\", config\", \"app\", \"atu\";\n>> linux,pci-domain = <0>;\n>> max-link-speed = <4>;\n>> bus-range = <0x00 0x08>;\n>> \n>> --\n>> 2.47.3\n>>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=temperror header.d=dev.tdt.de header.i=@dev.tdt.de header.a=rsa-sha256\n header.s=z1-selector1 header.b=aEvjZUmV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52552-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de\n header.b=\"aEvjZUmV\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=194.37.255.70","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=dev.tdt.de","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=dev.tdt.de"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwgNq09q7z1yHM\n\tfor ; Wed, 15 Apr 2026 22:26:19 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 7F657306BFFE\n\tfor ; Wed, 15 Apr 2026 12:26:15 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 59A1928CF6F;\n\tWed, 15 Apr 2026 12:26:14 +0000 (UTC)","from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BE6426A0B9;\n\tWed, 15 Apr 2026 12:26:12 +0000 (UTC)","from [194.37.255.9] (helo=mxout.expurgate.net)\n\tby relay.expurgate.net with smtp (Exim 4.92)\n\t(envelope-from )\n\tid 1wCzJq-003mcy-EM; Wed, 15 Apr 2026 14:26:10 +0200","from [195.243.126.94] (helo=securemail.tdt.de)\n\tby relay.expurgate.net with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256)\n\t(Exim 4.92)\n\t(envelope-from )\n\tid 1wCzJp-001aHb-SV; Wed, 15 Apr 2026 14:26:09 +0200","from securemail.tdt.de (localhost [127.0.0.1])\n\tby securemail.tdt.de (Postfix) with ESMTP id 78F18240042;\n\tWed, 15 Apr 2026 14:26:09 +0200 (CEST)","from mail.dev.tdt.de (unknown [10.2.4.42])\n\tby securemail.tdt.de (Postfix) with ESMTP id 5B894240040;\n\tWed, 15 Apr 2026 14:26:09 +0200 (CEST)","from mail.dev.tdt.de (localhost [IPv6:::1])\n\tby mail.dev.tdt.de (Postfix) with ESMTP id F003E23F75;\n\tWed, 15 Apr 2026 14:26:08 +0200 (CEST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776255974; cv=none;\n b=nYBfiMhhhMLVyXXnt/3Qva7tAY4ea1bQ5dqTgeIWtTs6QVdqMVB0yseiGztMlZ3RGqnljcLtoue4TA1a6CKeKPO5eyX5/NRa5EzaXC27kykKncUTvjoCyofypLmBmKWwUykfC4PvFMxX/bV7RMa1j3RWRuIE7CgSkOxccCYfXYU=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776255974; c=relaxed/simple;\n\tbh=Li63j71Mljod26r9+ICoxbjyS0KibXjBkSrFkDDhNmw=;\n\th=MIME-Version:Content-Type:Date:From:To:Cc:Subject:In-Reply-To:\n\t References:Message-ID;\n b=qy1ZfVbN0EthH6H7YX50bIYN9Mj/qj3utfUOlke9mC2Rh4iFjBVHwwxjxYhMrjbm+Az9R5Xmc48MwBfe9Da9N2eSdZjgxHAJqt2cXGZ59edaN5lUf2JB/I0WFkHFJ8WD/uq0YAsuoejBi6CM0mfjg8IY9L7hmpzDxt0YVZOem8Q=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=dev.tdt.de;\n spf=pass smtp.mailfrom=dev.tdt.de;\n dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de\n header.b=aEvjZUmV; arc=none smtp.client-ip=194.37.255.70","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=dev.tdt.de;\n\ts=z1-selector1; t=1776255969;\n\tbh=P9F+Tlb4TGrVTlb8Ne7lydILYvERL367bJz/FgB5ffQ=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:References:From;\n\tb=aEvjZUmVevov5inqXPlRwb4l1ReAK8H0uJDyDi1swElMLvCBimpdlAu4MInooGzet\n\t V/Hrx1BL+xZQFDEZmW5gmwAkrKNIMdhHcl7AkCmAVU63UCAPKxZxETOMvlVGZUAK7u\n\t rIBfpyCo6mmHKWB9p0xpMbMWC9mrCvboTGTxpzIwayEV4TRuCVBbe+TWpJWUQXRZyf\n\t MubRhC1ia2gGS06pGCo56DmHmeeoSHKBmBpAERMwyUl0OBNEnCdfGLy9Y/pbQzqLkm\n\t Rgr2qq2GQYMLod5q6HoeW/FAozEpBC0TX8xrIG0F+M2v+MCuDgp1/CUatJE+oq4fGu\n\t 0Zr7s/IHTrzkg==","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8;\n format=flowed","Date":"Wed, 15 Apr 2026 14:26:08 +0200 (CEST)","From":"Florian Eckert ","To":"Rob Herring ","Cc":"Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Bjorn Helgaas ,\n Johan Hovold , Sajid Dalvi ,\n Ajay Agarwal ,\n Krzysztof Kozlowski , Conor Dooley ,\n linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n devicetree@vger.kernel.org, Eckert.Florian@googlemail.com, ms@dev.tdt.de","Subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu\n resource","In-Reply-To":"\n ","References":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>\n <20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de>\n ","Message-ID":"","X-Sender":"fe@dev.tdt.de","User-Agent":"Roundcube Webmail/1.3.17","Content-Transfer-Encoding":"quoted-printable","X-purgate":"clean","X-purgate-ID":"151534::1776255970-6EEFEC78-9BEA26FC/0/0","X-purgate-type":"clean"}},{"id":3677640,"web_url":"http://patchwork.ozlabs.org/comment/3677640/","msgid":"","list_archive_url":null,"date":"2026-04-15T12:46:31","subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu resource","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Wed, Apr 15, 2026 at 7:26 AM Florian Eckert wrote:\n>\n>\n>\n> On 2026-04-15 14:09, Rob Herring wrote:\n> > On Wed, Apr 15, 2026 at 3:02 AM Florian Eckert wrote:\n> >>\n> >> The 'atu' information is already set in the dwc core, if it is\n> >> specified\n> >> in the devicetree. The driver uses its own default, if not set in the\n> >> devicetree. This information is hardware specific and should therefore\n> >> be\n> >> maintained in the devicetree rather than in the source.\n> >>\n> >> To be backward compatible, this field is not mandatory. If 'atu'\n> >> resource is not specified in the devicetree, the driver’s default\n> >> value\n> >> is used.\n> >>\n> >> Signed-off-by: Florian Eckert \n> >> ---\n> >> Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 8 ++++++--\n> >> 1 file changed, 6 insertions(+), 2 deletions(-)\n> >>\n> >> diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n> >> b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n> >> index\n> >> 54e2890ae6314ac6847fc23f49440d05d66d87d4..9b7a8ef77585677841c7064c5001110bc2b65db1\n> >> 100644\n> >> --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n> >> +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml\n> >> @@ -27,16 +27,19 @@ properties:\n> >> - const: snps,dw-pcie\n> >>\n> >> reg:\n> >> + minItems: 3\n> >> items:\n> >> - description: Controller control and status registers.\n> >> - description: PCIe configuration registers.\n> >> - description: Controller application registers.\n> >> + - description: Internal Address Translation Unit (iATU)\n> >> registers.\n> >>\n> >> reg-names:\n> >\n> > Don't you need minItems here?\n>\n> You're absolutely right, of course!\n> My fault. Thanks for pointing that out.\n> I will wait 24 hours to send a v5 with this change.\n>\n> Just to clarify. How does the creator of DTS know which items are\n> required.\n> Does that mean, in this case, that the last item is always optional and\n> the\n> others are absolutely essential?\n\nCorrect. There is no way in json-schema to express some entry in the\nmiddle of an 'items' list is optional.\n\nRob","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=NAML3OpY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-52553-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"NAML3OpY\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwgrp6gZJz1yDF\n\tfor ; Wed, 15 Apr 2026 22:47:06 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 5A5E4300404B\n\tfor ; Wed, 15 Apr 2026 12:46:46 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 96AF22512C8;\n\tWed, 15 Apr 2026 12:46:44 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 73D52823DD\n\tfor ; Wed, 15 Apr 2026 12:46:44 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 43714C2BCB9\n\tfor ; Wed, 15 Apr 2026 12:46:44 +0000 (UTC)","by mail-ed1-f54.google.com with SMTP id\n 4fb4d7f45d1cf-671dad7cac8so3164161a12.0\n for ; Wed, 15 Apr 2026 05:46:44 -0700 (PDT)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776257204; cv=none;\n b=jBnkwLXxgZJ/cTdQqnNKto6U8ZtlrCqLWEa9XO+dlOgb6Es4tzP0342zWesXNwcZD9qKPnyZqpwj/b/qVmKQNzd0cMT4ASmO5EeQCdPkvGIz/KRDocLRoxA5z46+eqCog/u0BdAOb/dbzzNDE7s0kZDCwo4N6hatVsjunA6nANA=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776257204; c=relaxed/simple;\n\tbh=y6aTsiofXPOnvztdKrV8k2Ec2I+P5cQybhcJwQvOeog=;\n\th=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:\n\t To:Cc:Content-Type;\n b=vERFIgMJkSpd1hUyV4MnH1dBd9R5uisP77Oj+j20G1epUEBSXzG/Na4PeRTPLF66En3tiugpqMpOh3Ic9uUYbPFlzzSX68D2WUE1vEYtOgzm101ljaQIE9CM6bUcvYaPETvO5f81+XX3mPSEUwm7XJ0rvTJAldBYpcQJJ590Anc=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=NAML3OpY; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1776257204;\n\tbh=y6aTsiofXPOnvztdKrV8k2Ec2I+P5cQybhcJwQvOeog=;\n\th=References:In-Reply-To:From:Date:Subject:To:Cc:From;\n\tb=NAML3OpY1TjcqVX13hlsUO4T7/EL7/87EQccArfc3DzyT8jArSkr39Y6zqOQnkLjv\n\t UJCc+lARrNpX3YXcSYl3Fyrue153+6GLKrz6zxXYGBja8FTdA3Wj9Ed/fce9yLyGzr\n\t QMCgQBVKjcXwnr172m2TvTdUrjIKYBLpoOLbBoAjiHp75BBXenY8pVpLBYmk+mczne\n\t Yyr5HMyJwrzyYzyyry6ygT59/QKLVob0ju5sJfahkezQ3VlxXaJwYM4/UDkH9YXZhC\n\t xmlLQl11NLPvG9Dgpt934BQgS+vjfm8EO/vka/2Vti6nQ4Zh27AiMOuBC5rmne0BXA\n\t TNmEAsePtwl3g==","X-Forwarded-Encrypted":"i=1;\n AFNElJ9+T4cx7P8G1kHBpgoB2KGiA2QFiHlpNTGaKTRQw6bZ0gyBXFvzAJl9t7tyJOo8YAslj6M8i0Qj5Yk=@vger.kernel.org","X-Gm-Message-State":"AOJu0YwzdyTjpc2bm4S9Pwy34/2XBLfBhHoQLYzNxdbqNnZxdK7+HAX2\n\tm/gcbPjOlH/vX7zJGP5ze7DhnXq9xEkOJMpD5JBtWIgZyvvKyPMxxh+YXuJzqkbiael8TnaUOa2\n\tAV0m/QLOilKiSUyKms7RM3AuUMKyjeQ==","X-Received":"by 2002:a05:6402:280b:b0:66e:37b0:f802 with SMTP id\n 4fb4d7f45d1cf-6707aa4840fmr10497971a12.21.1776257202551; Wed, 15 Apr 2026\n 05:46:42 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>\n <20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de>\n \n ","In-Reply-To":"","From":"Rob Herring ","Date":"Wed, 15 Apr 2026 07:46:31 -0500","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AQROBzAxKS5TTJOZJvS_S6XVlD4QyCz8G2jrW7sy2RQ1KlCNgne8zOM4PFaLeqU","Message-ID":"\n ","Subject":"Re: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu resource","To":"Florian Eckert ","Cc":"Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam ,\n Bjorn Helgaas , Johan Hovold ,\n Sajid Dalvi , Ajay Agarwal ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Eckert.Florian@googlemail.com, ms@dev.tdt.de","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}}]