[{"id":3677703,"web_url":"http://patchwork.ozlabs.org/comment/3677703/","msgid":"<20260415-craving-rubbing-bc8d389d19de@spud>","list_archive_url":null,"date":"2026-04-15T14:28:18","subject":"Re: [PATCH v3 1/3] riscv: add UltraRISC SoC family Kconfig support","submitter":{"id":84372,"url":"http://patchwork.ozlabs.org/api/people/84372/","name":"Conor Dooley","email":"conor@kernel.org"},"content":"On Wed, Apr 15, 2026 at 03:21:17PM +0800, Jia Wang wrote:\n> The first SoC in the UltraRISC series is UR-DP1000, containing octa\n> UltraRISC CP100 cores.\n> \n> Signed-off-by: Jia Wang \n\nAcked-by: Conor Dooley \n\n> ---\n> arch/riscv/Kconfig.socs | 6 ++++++\n> 1 file changed, 6 insertions(+)\n> \n> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs\n> index d621b85dd63b..0b4d06a7b4bf 100644\n> --- a/arch/riscv/Kconfig.socs\n> +++ b/arch/riscv/Kconfig.socs\n> @@ -84,6 +84,12 @@ config ARCH_THEAD\n> \thelp\n> \t This enables support for the RISC-V based T-HEAD SoCs.\n> \n> +config ARCH_ULTRARISC\n> +\tbool \"UltraRISC RISC-V SoCs\"\n> +\thelp\n> +\t This enables support for UltraRISC SoC platform hardware,\n> +\t including boards based on the UR-DP1000.\n> +\n> config ARCH_VIRT\n> \tbool \"QEMU Virt Machine\"\n> \tselect POWER_RESET\n> \n> -- \n> 2.34.1\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=H/YX+RVR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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