[{"id":3677870,"web_url":"http://patchwork.ozlabs.org/comment/3677870/","msgid":"","list_archive_url":null,"date":"2026-04-16T00:07:35","subject":"Re: [PATCH v2 4/4] hw/riscv/boot: Provide a simple halting payload","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Apr 15, 2026 at 4:50 PM Joel Stanley wrote:\n>\n> From: Nicholas Piggin \n>\n> OpenSBI hangs before any console output if the domain init code sees the\n> next stage is not in an executable region.\n>\n> If no kernel payload is provided to QEMU, the next stage address is\n> NULL, and the riscv virt machine memory map ends up covering the 0\n> address with the catch all S-mode RWX region and so OpenSBI prints\n> console messages and does not hang until the next stage boot.\n>\n> The soon to be added Tenstorrent Atlantis board address map has RAM\n> starting at 0 and it loads OpenSBI there, so it is M-mode and not\n> accessible by S-mode, tripping the early check and hang.\n\nThat sounds like an OpenSBI bug more than a hardware/QEMU issue.\n\n>\n> Add a helper to set up a simple payload that gets OpenSBI messages\n> to console.\n\nWhere do we load this payload? What happens if the user loads\nsomething there as well, so we clobber their binary?\n\nThis seems like something that should be fixed in OpenSBI instead of\nhacked around in QEMU\n\n>\n> Signed-off-by: Nicholas Piggin \n> Reviewed-by: Daniel Henrique Barboza \n> Signed-off-by: Joel Stanley \n> ---\n> v2: Update commit message to clarfiy that Atlantis isn't in the tree yet\n>\n> include/hw/riscv/boot.h | 2 ++\n> hw/riscv/boot.c | 21 +++++++++++++++++++++\n> 2 files changed, 23 insertions(+)\n>\n> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\n> index fb90bf12399e..d1d7258a2179 100644\n> --- a/include/hw/riscv/boot.h\n> +++ b/include/hw/riscv/boot.h\n> @@ -78,6 +78,8 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts\n> hwaddr rom_base, hwaddr rom_size,\n> uint64_t kernel_entry,\n> uint64_t fdt_load_addr);\n> +void riscv_setup_halting_payload(MachineState *machine,\n> + RISCVBootInfo *info, hwaddr addr);\n> void riscv_rom_copy_firmware_info(MachineState *machine,\n> RISCVHartArrayState *harts,\n> hwaddr rom_base,\n> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\n> index 3ea95c175c14..fc8a39a8d913 100644\n> --- a/hw/riscv/boot.c\n> +++ b/hw/riscv/boot.c\n> @@ -518,6 +518,27 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts\n> kernel_entry);\n> }\n>\n> +/* Simple payload so OpenSBI does not hang early with no output */\n> +void riscv_setup_halting_payload(MachineState *machine,\n> + RISCVBootInfo *info, hwaddr addr)\n\nThis function is currently unused as well\n\nAlistair\n\n> +{\n> + int i;\n> + uint32_t payload_vec[] = {\n> + 0x10500073, /* 1: wfi */\n> + 0xffdff06f, /* j 1b */\n> + };\n> + /* copy in the payload vector in little_endian byte order */\n> + for (i = 0; i < ARRAY_SIZE(payload_vec); i++) {\n> + payload_vec[i] = cpu_to_le32(payload_vec[i]);\n> + }\n> + rom_add_blob_fixed_as(\"mrom.payload\", payload_vec, sizeof(payload_vec),\n> + addr, &address_space_memory);\n> +\n> + info->kernel_size = sizeof(payload_vec);\n> + info->image_low_addr = addr;\n> + info->image_high_addr = info->image_low_addr + info->kernel_size;\n> +}\n> +\n> void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)\n> {\n> CPUState *cs;\n> --\n> 2.47.3\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=jJtBys8S;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwyz16r4tz1yHP\n\tfor ; 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Wed, 15 Apr 2026\n 17:08:04 -0700 (PDT)","MIME-Version":"1.0","References":"<20260415064838.652297-1-joel@jms.id.au>\n <20260415064838.652297-5-joel@jms.id.au>","In-Reply-To":"<20260415064838.652297-5-joel@jms.id.au>","From":"Alistair Francis ","Date":"Thu, 16 Apr 2026 10:07:35 +1000","X-Gm-Features":"AQROBzCW8dBcAsMfWD7bEGxxLt9aaTLgdiQ_ksRAhI52m84iojiEsGUv3NCoBc0","Message-ID":"\n ","Subject":"Re: [PATCH v2 4/4] hw/riscv/boot: Provide a simple halting payload","To":"Joel Stanley ","Cc":"Alistair Francis ,\n Daniel Henrique Barboza ,\n qemu-devel@nongnu.org,\n Nicholas Piggin , Weiwei Li ,\n Michael Ellerman ,\n Joel Stanley ,\n Nick Piggin ,\n Anirudh Srinivasan , qemu-riscv@nongnu.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2607:f8b0:4864:20::b133;\n envelope-from=alistair23@gmail.com; helo=mail-yx1-xb133.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]