[{"id":3677299,"web_url":"http://patchwork.ozlabs.org/comment/3677299/","msgid":"<32594f82-0268-4844-830a-4147bd1598f6@redhat.com>","list_archive_url":null,"date":"2026-04-14T16:10:19","subject":"Re: [PATCH v4 8/9] target/i386/mshv: filter out CET bits in cpuid","submitter":{"id":2701,"url":"http://patchwork.ozlabs.org/api/people/2701/","name":"Paolo Bonzini","email":"pbonzini@redhat.com"},"content":"On 4/14/26 17:54, Magnus Kulke wrote:\n> e46dcef1d0 introduced CET_U/CET_S xstate bits in the ExtSaveArea. The\n> response in EBX of a 0x4,1 cpuid query will contain a size contingent on\n> what the guest enabled in the IA32_XSS MSR (compacted xsave size).\n> \n> Since the MSHV accelerator currently responds with static answers to\n> 0x4d cpuid queries, we'll have to disable those bits, even if the host\n> supports them.\n> \n> Signed-off-by: Magnus Kulke \n> Reviewed-by: Anirudh Rayabharam (Microsoft) \n> ---\n> target/i386/mshv/mshv-cpu.c | 19 +++++++++++++++++++\n> 1 file changed, 19 insertions(+)\n> \n> diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\n> index ee25eb5f6f..2c66a52709 100644\n> --- a/target/i386/mshv/mshv-cpu.c\n> +++ b/target/i386/mshv/mshv-cpu.c\n> @@ -1663,6 +1663,25 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uint32_t idx, int reg)\n> if (func == 0x01 && reg == R_ECX) {\n> ret &= ~CPUID_EXT_VMX;\n> }\n> +\n> + /*\n> + * MSHV currently uses static CPUID intercept results for leaf 0xD.\n> + * However there are feature-responses that are dynamic based on what a\n> + * guest enables in XCR0 and XSS, such as CET shadow stack.\n> + *\n> + * A guest which doesn't know about those features yet would encounter an\n> + * unexpcted CPUID[0xD,1].EBX (compactes XSAVE size) and either fail\n> + * or gracefully degrade by not using XSAVE at all.\n> + *\n> + * To avoid this, we filter out supervisor xstate features.\n> + */\n\nI don't understand this, but it seems to be a Linux bug. Don't *all* \nxsave features cause changes to CPUID[0xD,1].EBX?\n\nPaolo\n\n> + if (func == 0x07 && idx == 0 && reg == R_ECX) {\n> + ret &= ~CPUID_7_0_ECX_CET_SHSTK;\n> + }\n> + if (func == 0x07 && idx == 0 && reg == R_EDX) {\n> + ret &= ~CPUID_7_0_EDX_CET_IBT;\n> + }\n> +\n> return ret;\n> }\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=dJk9RyUH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fw8QR5Dwyz1xtJ\n\tfor ; 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