[{"id":3677536,"web_url":"http://patchwork.ozlabs.org/comment/3677536/","msgid":"<42bdc5ab-1c67-46f4-955c-d86ffd2706ec@linux.ibm.com>","list_archive_url":null,"date":"2026-04-15T08:49:08","subject":"Re: [PATCH v2] rs6000: Fix PTImode attribute handling [PR106895]","submitter":{"id":88474,"url":"http://patchwork.ozlabs.org/api/people/88474/","name":"Surya Kumari Jangala","email":"jskumari@linux.ibm.com"},"content":"The patch looks fine to me. I cannot approve it though.\n\n-Surya\n\nOn 14/04/26 5:04 PM, jeevitha wrote:\n> Hi All,\n> \n> The following patch has been bootstrapped and regtested on powerpc64le-linux.\n> \n> Changes from V1:\n> * Added new test pr106895-2.c.\n> \n> PTImode is used to generate even/odd register pairs for 128-bit values.\n> When PTImode is specified via a type attribute, compilation fails\n> because no internal type exists to represent this mode.\n> \n> Introduce signed and unsigned PTImode internal builtin types to handle\n> PTImode. These __pti_internal types are not documented, as they are not\n> intended for direct user use.\n> \n> 2026-04-14 Jeevitha Palanisamy \n> \n> gcc/\n> \tPR target/106895\n> \t* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add\n> \tRS6000_BTI_INTPTI and RS6000_BTI_UINTPTI.\n> \t(intPTI_type_internal_node, uintPTI_type_internal_node): New\n> \tPTImode type macros.\n> \t* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Register\n> \tsigned and unsigned PTImode internal builtin types.\n> \t* config/rs6000/sync.md (trunctipti2): New splitter.\n> \t(extendptiti2): Likewise.\n> \t(zero_extendptiti2): Likewise.\n> \n> gcc/testsuite/\n> \tPR target/106895\n> \t* gcc.target/powerpc/pr106895-1.c: New test.\n> \t* gcc.target/powerpc/pr106895-2.c: New test.\n> \n> diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc\n> index bbf60de3b1b..8561cd67f53 100644\n> --- a/gcc/config/rs6000/rs6000-builtin.cc\n> +++ b/gcc/config/rs6000/rs6000-builtin.cc\n> @@ -756,6 +756,19 @@ rs6000_init_builtins (void)\n> else\n> ieee128_float_type_node = NULL_TREE;\n> \n> + /* PTImode to get even/odd register pairs. */\n> + intPTI_type_internal_node = make_signed_type (GET_MODE_BITSIZE (PTImode));\n> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);\n> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);\n> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,\n> +\t\t\t\t\t \"__pti_internal\");\n> +\n> + uintPTI_type_internal_node = make_unsigned_type (GET_MODE_BITSIZE (PTImode));\n> + SET_TYPE_MODE (uintPTI_type_internal_node, PTImode);\n> + t = build_qualified_type (uintPTI_type_internal_node, TYPE_QUAL_CONST);\n> + lang_hooks.types.register_builtin_type (uintPTI_type_internal_node,\n> +\t\t\t\t\t \"__upti_internal\");\n> +\n> /* Vector pair and vector quad support. */\n> vector_pair_type_node = make_node (OPAQUE_TYPE);\n> SET_TYPE_MODE (vector_pair_type_node, OOmode);\n> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\n> index 2b90694cef1..d85f71aa65d 100644\n> --- a/gcc/config/rs6000/rs6000.h\n> +++ b/gcc/config/rs6000/rs6000.h\n> @@ -2285,6 +2285,8 @@ enum rs6000_builtin_type_index\n> RS6000_BTI_ptr_vector_quad,\n> RS6000_BTI_ptr_long_long,\n> RS6000_BTI_ptr_long_long_unsigned,\n> + RS6000_BTI_INTPTI,\n> + RS6000_BTI_UINTPTI,\n> RS6000_BTI_MAX\n> };\n> \n> @@ -2329,6 +2331,8 @@ enum rs6000_builtin_type_index\n> #define uintDI_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_UINTDI])\n> #define intTI_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_INTTI])\n> #define uintTI_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_UINTTI])\n> +#define intPTI_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_INTPTI])\n> +#define uintPTI_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_UINTPTI])\n> #define float_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_float])\n> #define double_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_double])\n> #define long_double_type_internal_node\t (rs6000_builtin_types[RS6000_BTI_long_double])\n> diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md\n> index 7087daf7e4c..4e392584bbc 100644\n> --- a/gcc/config/rs6000/sync.md\n> +++ b/gcc/config/rs6000/sync.md\n> @@ -198,6 +198,54 @@\n> DONE;\n> })\n> \n> +;; PTI and TI are both 128-bit modes; the following conversions are\n> +;; register-class changes only, no actual truncation, sign or zero\n> +;; extension occurs.\n> +(define_insn_and_split \"trunctipti2\"\n> + [(set (match_operand:PTI 0 \"register_operand\" \"=r\")\n> + (truncate:PTI (match_operand:TI 1 \"register_operand\" \"r\")))]\n> + \"\"\n> + \"#\"\n> + \"&& reload_completed\"\n> + [(set (match_dup 2) (match_dup 4))\n> + (set (match_dup 3) (match_dup 5))]\n> +{\n> + operands[2] = gen_lowpart (DImode, operands[0]);\n> + operands[3] = gen_highpart (DImode, operands[0]);\n> + operands[4] = gen_lowpart (DImode, operands[1]);\n> + operands[5] = gen_highpart (DImode, operands[1]);\n> +})\n> +\n> +(define_insn_and_split \"extendptiti2\"\n> + [(set (match_operand:TI 0 \"register_operand\" \"=r\")\n> + (sign_extend:TI (match_operand:PTI 1 \"register_operand\" \"r\")))]\n> + \"\"\n> + \"#\"\n> + \"&& reload_completed\"\n> + [(set (match_dup 2) (match_dup 4))\n> + (set (match_dup 3) (match_dup 5))]\n> +{\n> + operands[2] = gen_lowpart (DImode, operands[0]);\n> + operands[3] = gen_highpart (DImode, operands[0]);\n> + operands[4] = gen_lowpart (DImode, operands[1]);\n> + operands[5] = gen_highpart (DImode, operands[1]);\n> +})\n> +\n> +(define_insn_and_split \"zero_extendptiti2\"\n> + [(set (match_operand:TI 0 \"register_operand\" \"=r\")\n> + (zero_extend:TI (match_operand:PTI 1 \"register_operand\" \"r\")))]\n> + \"\"\n> + \"#\"\n> + \"&& reload_completed\"\n> + [(set (match_dup 2) (match_dup 4))\n> + (set (match_dup 3) (match_dup 5))]\n> +{\n> + operands[2] = gen_lowpart (DImode, operands[0]);\n> + operands[3] = gen_highpart (DImode, operands[0]);\n> + operands[4] = gen_lowpart (DImode, operands[1]);\n> + operands[5] = gen_highpart (DImode, operands[1]);\n> +})\n> +\n> ;; If TARGET_PREFIXED, always use pstq rather than stq.\n> (define_insn \"store_quadpti\"\n> [(set (match_operand:PTI 0 \"quad_memory_operand\" \"=wQ\")\n> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895-1.c b/gcc/testsuite/gcc.target/powerpc/pr106895-1.c\n> new file mode 100644\n> index 00000000000..dfcafcd57e7\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895-1.c\n> @@ -0,0 +1,16 @@\n> +/* PR target/106895 */\n> +/* { dg-do assemble } */\n> +/* { dg-require-effective-target int128 } */\n> +/* { dg-options \"-O2 -save-temps\" } */\n> +\n> +/* Verify the following generates even/odd register pairs. */\n> +\n> +typedef __int128 pti __attribute__((mode(PTI)));\n> +\n> +void\n> +set128 (pti val, pti *mem)\n> +{\n> + asm (\"stq %1,%0\" : \"=m\" (*mem) : \"r\" (val));\n> +}\n> +\n> +/* { dg-final { scan-assembler {\\mstq\\M} } } */\n> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895-2.c b/gcc/testsuite/gcc.target/powerpc/pr106895-2.c\n> new file mode 100644\n> index 00000000000..7a197ff65cf\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895-2.c\n> @@ -0,0 +1,21 @@\n> +/* PR target/106895 */\n> +/* { dg-do run } */\n> +/* { dg-require-effective-target int128 } */\n> +/* { dg-options \"-O2\" } */\n> +\n> +#include \n> +\n> +typedef __int128 ti;\n> +typedef __int128 pti __attribute__((mode(PTI)));\n> +\n> +int main(void)\n> +{\n> + ti a = 140;\n> + pti b = (pti) a;\n> + ti c = (ti) b;\n> +\n> + if (c != a)\n> + abort();\n> +\n> + return 0;\n> +}\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=eVQA7j8l;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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