[{"id":3677074,"web_url":"http://patchwork.ozlabs.org/comment/3677074/","msgid":"","list_archive_url":null,"date":"2026-04-14T08:46:17","subject":"Re: [PATCH] RISC-V: Make tuple vector not tieable to some modes.","submitter":{"id":86205,"url":"http://patchwork.ozlabs.org/api/people/86205/","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"content":"Hi Zicong,\n\nThanks for tackling this.\n\n> PR 124448\n\nThis is missing a \"target\", i.e. PR target/124448.\n\n> --- a/gcc/config/riscv/riscv.cc\n> +++ b/gcc/config/riscv/riscv.cc\n> @@ -10897,6 +10897,31 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)\n> E.g. V2SI and DI are not tieable. */\n> if (riscv_vector_mode_p (mode1) != riscv_vector_mode_p (mode2))\n> return false;\n> +\n> + /* We don't allow tuple vector modes to be tied to any vector mode\n> + that has different inner mode. It may cause unnecessary type\n> + conversions.\n> + E.g. RVVMF2x4HI and RVVM2DI are not tieable. */\n> + if (riscv_tuple_mode_p (mode1) || riscv_tuple_mode_p (mode2))\n> + {\n> + machine_mode subpart_mode1, subpart_mode2;\n> + if (riscv_tuple_mode_p (mode1))\n> + {\n> + subpart_mode1 = riscv_vector::get_subpart_mode (mode1);\n> + subpart_mode1 = GET_MODE_INNER (subpart_mode1);\n> + }\n> + else\n> + subpart_mode1 = GET_MODE_INNER (mode1);\n> + if (riscv_tuple_mode_p (mode2))\n> + {\n> + subpart_mode2 = riscv_vector::get_subpart_mode (mode2);\n> + subpart_mode2 = GET_MODE_INNER (subpart_mode2);\n> + }\n> + else\n> + subpart_mode2 = GET_MODE_INNER (mode2);\n> + if (subpart_mode1 != subpart_mode2)\n> + return false;\n> + }\n\nI wonder if we gain something from making similar inner modes tieable, i.e. \nRVVMF2x4HI and RVVMF4HI? Did you observe cases where this helps?\n\nPut differently, are there cases you want to handle that\n\n if (riscv_tuple_mode_p (mode1) != riscv_tuple_mode_p (mode2))\n return false;\n\ndoes not catch?\n\n> return (mode1 == mode2\n> \t || !(GET_MODE_CLASS (mode1) == MODE_FLOAT\n> \t && GET_MODE_CLASS (mode2) == MODE_FLOAT));\n> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n> new file mode 100644\n> index 00000000000..fd74c509849\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n> @@ -0,0 +1,37 @@\n> +/* { dg-do compile } */\n> +/* { dg-options \"-march=rv64gcv_zvl128b -O3 -mrvv-vector-bits=zvl\" } */\n\nHere you also need -mabi=lp64d for multilib settings.\n\n> +/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-O1\" \"-O2\" \"-Os\" \"-Og\" \"-Oz\" } } */\n\nI don't think this is necessary when you specify -O3 directly.\n\n\n> +#include \n\nYou could just use a\n typedef short int16_t;\ninstead of the include.\n\n> +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */\n> +/* { dg-final { scan-assembler-not {vslidedown\\.vi} } } */\n\nHow about something like\n/* { dg-final { scan-rtl-dump-not \"(subreg:RVVM2DI (reg:RVVMF2x4HI\" \"vregs\" } } */\non top, for a more targeted check?","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=QcIFoXjr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=UTF-8","Date":"Tue, 14 Apr 2026 10:46:17 +0200","Message-Id":"","Subject":"Re: [PATCH] RISC-V: Make tuple vector not tieable to some modes.","Cc":"\"Robin Dapp\" ","To":"\"wangzicong\" , ","From":"\"Robin Dapp\" ","References":"<20260414082141.763453-1-wangzicong@masscore.cn>","In-Reply-To":"<20260414082141.763453-1-wangzicong@masscore.cn>","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3677447,"web_url":"http://patchwork.ozlabs.org/comment/3677447/","msgid":"<006b01dccc8b$18ea9720$4abfc560$@masscore.cn>","list_archive_url":null,"date":"2026-04-15T03:51:09","subject":"RE: [PATCH] RISC-V: Make tuple vector not tieable to some modes.","submitter":{"id":93140,"url":"http://patchwork.ozlabs.org/api/people/93140/","name":"wangzicong","email":"wangzicong@masscore.cn"},"content":"Thanks Robin.\n\n> This is missing a \"target\", i.e. PR target/124448.\n\nOK.\n\n> I wonder if we gain something from making similar inner modes tieable, i.e.\n> RVVMF2x4HI and RVVMF4HI? Did you observe cases where this helps?\n> \n> Put differently, are there cases you want to handle that\n> \n> if (riscv_tuple_mode_p (mode1) != riscv_tuple_mode_p (mode2))\n> return false;\n> \n> does not catch?\n\nActually no other case. I just wonder with the same inner mode it may \nnot hurt. Maybe we should do as you suggest until we find a case.\n\n> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n> > @@ -0,0 +1,37 @@\n> > +/* { dg-do compile } */\n> > +/* { dg-options \"-march=rv64gcv_zvl128b -O3 -mrvv-vector-bits=zvl\" } */\n> \n> Here you also need -mabi=lp64d for multilib settings.\n> \n> > +/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-O1\" \"-O2\" \"-Os\" \"-Og\" \"-Oz\" } } */\n> \n> I don't think this is necessary when you specify -O3 directly.\n> \n> \n> > +#include \n> \n> You could just use a\n> typedef short int16_t;\n> instead of the include.\n> \n> > +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */\n> > +/* { dg-final { scan-assembler-not {vslidedown\\.vi} } } */\n> \n> How about something like\n> /* { dg-final { scan-rtl-dump-not \"(subreg:RVVM2DI (reg:RVVMF2x4HI\"\n> \"vregs\" } } */\n> on top, for a more targeted check?\n\nOK. Thanks.\n\nZicong\n\n> -----Original Message-----\n> From: Robin Dapp \n> Sent: 2026年4月14日 16:46\n> To: wangzicong ; gcc-patches@gcc.gnu.org\n> Cc: Robin Dapp \n> Subject: Re: [PATCH] RISC-V: Make tuple vector not tieable to some modes.\n> \n> Hi Zicong,\n> \n> Thanks for tackling this.\n> \n> > PR 124448\n> \n> This is missing a \"target\", i.e. PR target/124448.\n> \n> > --- a/gcc/config/riscv/riscv.cc\n> > +++ b/gcc/config/riscv/riscv.cc\n> > @@ -10897,6 +10897,31 @@ riscv_modes_tieable_p (machine_mode\n> mode1, machine_mode mode2)\n> > E.g. V2SI and DI are not tieable. */\n> > if (riscv_vector_mode_p (mode1) != riscv_vector_mode_p (mode2))\n> > return false;\n> > +\n> > + /* We don't allow tuple vector modes to be tied to any vector mode\n> > + that has different inner mode. It may cause unnecessary type\n> > + conversions.\n> > + E.g. RVVMF2x4HI and RVVM2DI are not tieable. */\n> > + if (riscv_tuple_mode_p (mode1) || riscv_tuple_mode_p (mode2))\n> > + {\n> > + machine_mode subpart_mode1, subpart_mode2;\n> > + if (riscv_tuple_mode_p (mode1))\n> > + {\n> > + subpart_mode1 = riscv_vector::get_subpart_mode (mode1);\n> > + subpart_mode1 = GET_MODE_INNER (subpart_mode1);\n> > + }\n> > + else\n> > + subpart_mode1 = GET_MODE_INNER (mode1);\n> > + if (riscv_tuple_mode_p (mode2))\n> > + {\n> > + subpart_mode2 = riscv_vector::get_subpart_mode (mode2);\n> > + subpart_mode2 = GET_MODE_INNER (subpart_mode2);\n> > + }\n> > + else\n> > + subpart_mode2 = GET_MODE_INNER (mode2);\n> > + if (subpart_mode1 != subpart_mode2)\n> > + return false;\n> > + }\n> \n> I wonder if we gain something from making similar inner modes tieable, i.e.\n> RVVMF2x4HI and RVVMF4HI? Did you observe cases where this helps?\n> \n> Put differently, are there cases you want to handle that\n> \n> if (riscv_tuple_mode_p (mode1) != riscv_tuple_mode_p (mode2))\n> return false;\n> \n> does not catch?\n> \n> > return (mode1 == mode2\n> > \t || !(GET_MODE_CLASS (mode1) == MODE_FLOAT\n> > \t && GET_MODE_CLASS (mode2) == MODE_FLOAT));\n> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n> > new file mode 100644\n> > index 00000000000..fd74c509849\n> > --- /dev/null\n> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n> > @@ -0,0 +1,37 @@\n> > +/* { dg-do compile } */\n> > +/* { dg-options \"-march=rv64gcv_zvl128b -O3 -mrvv-vector-bits=zvl\" } */\n> \n> Here you also need -mabi=lp64d for multilib settings.\n> \n> > +/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-O1\" \"-O2\" \"-Os\" \"-Og\" \"-Oz\" } } */\n> \n> I don't think this is necessary when you specify -O3 directly.\n> \n> \n> > +#include \n> \n> You could just use a\n> typedef short int16_t;\n> instead of the include.\n> \n> > +/* { dg-final { scan-assembler-times {vsetivli} 1 } } */\n> > +/* { dg-final { scan-assembler-not {vslidedown\\.vi} } } */\n> \n> How about something like\n> /* { dg-final { scan-rtl-dump-not \"(subreg:RVVM2DI (reg:RVVMF2x4HI\"\n> \"vregs\" } } */\n> on top, for a more targeted check?\n> \n> --\n> Regards\n> Robin","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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