[{"id":3677038,"web_url":"http://patchwork.ozlabs.org/comment/3677038/","msgid":"<5f0622a0-f42f-4f27-b457-cd13a23b316f@intel.com>","list_archive_url":null,"date":"2026-04-14T06:56:42","subject":"Re: [Intel-wired-lan] [PATCH iwl-net v3] e1000e: correct TIMINCA on\n ADP/TGP systems with wrong XTAL frequency","submitter":{"id":68688,"url":"http://patchwork.ozlabs.org/api/people/68688/","name":"Ruinskiy, Dima","email":"dima.ruinskiy@intel.com"},"content":"On 14/04/2026 9:51, Dima Ruinskiy wrote:\n> From: Vitaly Lifshits \n> \n> On some Tiger Lake (TGP) and Alder Lake (ADP) platforms, the hardware\n> XTAL clock is incorrectly interpreted as 24 MHz instead of the actual\n> 38.4 MHz. This causes the PHC to run significantly faster than system\n> time, breaking PTP synchronization.\n> \n> To mitigate this at runtime, measure PHC vs system time over ~1 ms using\n> cross-timestamps. If the PHC increment differs from system time beyond\n> the expected tolerance (currently >100 uSecs), reprogram TIMINCA for the\n> 38.4 MHz profile and reinitialize the timecounter.\n> \n> Tested on an affected system using phc_ctl:\n> Without fix:\n> sudo phc_ctl enp0s31f6 set 0.0 wait 10 get\n> clock time: 16.000541250 (expected ~10s)\n> \n> With fix:\n> sudo phc_ctl enp0s31f6 set 0.0 wait 10 get\n> clock time: 9.984407212 (expected ~10s)\n> \n> Fixes: fb776f5d57ee (\"e1000e: Add support for Tiger Lake\")\n> Signed-off-by: Vitaly Lifshits \n> Co-developed-by: Dima Ruinskiy \n> Signed-off-by: Dima Ruinskiy \n> ---\n> v4: replace ktime_to_ns(ktime_get_real()) with ktime_get_real_ns()\n> v3: fix cc.shift and wrap TIMINCA write in systim_lock\n> v2: avoid resetting the systim and rephrase commit message\n> v1: initial version\n> ---\n> drivers/net/ethernet/intel/e1000e/netdev.c | 78 ++++++++++++++++++++++\n> 1 file changed, 78 insertions(+)\n> \n> diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c\n> index 9befdacd6730..26fdef6075c8 100644\n> --- a/drivers/net/ethernet/intel/e1000e/netdev.c\n> +++ b/drivers/net/ethernet/intel/e1000e/netdev.c\n> @@ -3902,6 +3902,81 @@ static void e1000_flush_desc_rings(struct e1000_adapter *adapter)\n> \t\te1000_flush_rx_ring(adapter);\n> }\n> \n> +/**\n> + * e1000e_xtal_tgp_workaround - Adjust XTAL clock based on PHC and system\n> + * clock delta.\n> + * @adapter: Pointer to the private adapter structure\n> + *\n> + * Measures the time difference between the PHC (Precision Hardware Clock)\n> + * and the system clock over a 1 millisecond interval. If the delta\n> + * exceeds 100 microseconds, reconfigure the XTAL clock to 38.4 MHz.\n> + */\n> +static void e1000e_xtal_tgp_workaround(struct e1000_adapter *adapter)\n> +{\n> +\ts64 phc_delta, sys_delta, sys_start_ns, sys_end_ns, delta_ns;\n> +\tstruct ptp_system_timestamp sys_start = {}, sys_end = {};\n> +\tstruct ptp_clock_info *info = &adapter->ptp_clock_info;\n> +\tstruct timespec64 phc_start, phc_end;\n> +\tstruct e1000_hw *hw = &adapter->hw;\n> +\tstruct netlink_ext_ack extack = {};\n> +\tunsigned long flags;\n> +\tu32 timinca;\n> +\ts32 ret_val;\n> +\n> +\t/* Capture start */\n> +\tif (info->gettimex64(info, &phc_start, &sys_start)) {\n> +\t\te_dbg(\"PHC gettimex(start) failed\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\t/* Small interval to measure increment */\n> +\tusleep_range(1000, 1100);\n> +\n> +\t/* Capture end */\n> +\tif (info->gettimex64(info, &phc_end, &sys_end)) {\n> +\t\te_dbg(\"PHC gettimex(end) failed\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\t/* Compute deltas */\n> +\tphc_delta = timespec64_to_ns(&phc_end) -\n> +\t\t timespec64_to_ns(&phc_start);\n> +\n> +\tsys_start_ns = (timespec64_to_ns(&sys_start.pre_ts) +\n> +\t\t\ttimespec64_to_ns(&sys_start.post_ts)) >> 1;\n> +\n> +\tsys_end_ns = (timespec64_to_ns(&sys_end.pre_ts) +\n> +\t\t timespec64_to_ns(&sys_end.post_ts)) >> 1;\n> +\n> +\tsys_delta = sys_end_ns - sys_start_ns;\n> +\n> +\tdelta_ns = phc_delta - sys_delta;\n> +\tif (delta_ns > 100000) {\n> +\t\te_dbg(\"Corrected PHC frequency: TIMINCA set for 38.4 MHz\\n\");\n> +\t\t/* Program TIMINCA for 38.4 MHz */\n> +\t\tspin_lock_irqsave(&adapter->systim_lock, flags);\n> +\t\tadapter->cc.shift = INCVALUE_SHIFT_38400KHZ;\n> +\t\ttiminca = (INCPERIOD_38400KHZ <<\n> +\t\t\t E1000_TIMINCA_INCPERIOD_SHIFT) |\n> +\t\t\t (((INCVALUE_38400KHZ <<\n> +\t\t\t adapter->cc.shift) &\n> +\t\t\t E1000_TIMINCA_INCVALUE_MASK));\n> +\t\tew32(TIMINCA, timinca);\n> +\n> +\t\t/* reset the systim ns time counter */\n> +\t\ttimecounter_init(&adapter->tc, &adapter->cc,\n> +\t\t\t\t ktime_get_real_ns());\n> +\t\tspin_unlock_irqrestore(&adapter->systim_lock, flags);\n> +\n> +\t\t/* restore the previous hwtstamp configuration settings */\n> +\t\tret_val = e1000e_config_hwtstamp(adapter,\n> +\t\t\t\t\t\t &adapter->hwtstamp_config,\n> +\t\t\t\t\t\t &extack);\n> +\t\tif (ret_val && extack._msg)\n> +\t\t\te_err(\"%s\\n\", extack._msg);\n> +\t}\n> +}\n> +\n> /**\n> * e1000e_systim_reset - reset the timesync registers after a hardware reset\n> * @adapter: board private structure\n> @@ -3953,6 +4028,9 @@ static void e1000e_systim_reset(struct e1000_adapter *adapter)\n> \t\tif (extack._msg)\n> \t\t\te_err(\"%s\\n\", extack._msg);\n> \t}\n> +\n> +\tif (hw->mac.type == e1000_pch_adp || hw->mac.type == e1000_pch_tgp)\n> +\t\te1000e_xtal_tgp_workaround(adapter);\n> }\n> \n> /**\nOops, wrong title. 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