[{"id":3677187,"web_url":"http://patchwork.ozlabs.org/comment/3677187/","msgid":"<908b1360-e53d-4f33-82ce-4e2b67ddcfb7@linaro.org>","list_archive_url":null,"date":"2026-04-14T12:58:57","subject":"Re: [PATCH v3 15/21] drm/panel: jadard-jd9365da-h3: support Waveshare\n WXGA DSI panels","submitter":{"id":84903,"url":"http://patchwork.ozlabs.org/api/people/84903/","name":"Neil Armstrong","email":"neil.armstrong@linaro.org"},"content":"On 4/13/26 16:05, Dmitry Baryshkov wrote:\n> Add configuration for several Waveshare 8.0\" and 10.1\" WXGA DSI panels\n> using JD9365 controller\n> \n> Tested-by: Riccardo Mereu \n> Signed-off-by: Dmitry Baryshkov \n> ---\n> drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 568 +++++++++++++++++++++++\n> 1 file changed, 568 insertions(+)\n> \n> diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n> index 61d67efed379..7744c66514c9 100644\n> --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n> +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n> @@ -2067,6 +2067,566 @@ static const struct jadard_panel_desc waveshare_4_0_inch_c_desc = {\n> \t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n> };\n> \n> +static int waveshare_8_0_a_init(struct jadard *jadard)\n> +{\n> +\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x00);\n> +\tjadard_enable_standard_cmds(&dsi_ctx);\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n> +\tif (jadard->dsi->lanes == 4)\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7e);\n> +\telse\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x4e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xb7);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xb7);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x70);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x37);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x78);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x63);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x54);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3d);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x57);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x49);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x37);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x23);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x10);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3d);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x50);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x57);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x49);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10);\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x5f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x4a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x4a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x48);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x48);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x40);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0c);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x56);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xf8);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x03);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x03);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x7b);\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x2a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);\n> +\tif (jadard->dsi->lanes != 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n> +\t}\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x00);\n> +\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n> +\tmsleep(120);\n> +\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n> +\tmsleep(60);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static const struct drm_display_mode waveshare_8_0_a_mode = {\n> +\t.clock\t\t= (800 + 40 + 20 + 20) * (1280 + 30 + 12 + 4) * 60 / 1000,\n> +\n> +\t.hdisplay\t= 800,\n> +\t.hsync_start\t= 800 + 40,\n> +\t.hsync_end\t= 800 + 40 + 20,\n> +\t.htotal\t\t= 800 + 40 + 20 + 20,\n> +\n> +\t.vdisplay\t= 1280,\n> +\t.vsync_start\t= 1280 + 30,\n> +\t.vsync_end\t= 1280 + 30 + 12,\n> +\t.vtotal\t\t= 1280 + 30 + 12 + 4,\n> +\n> +\t.width_mm\t= 107,\n> +\t.height_mm\t= 172,\n> +\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n> +};\n> +\n> +static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {\n> +\t.mode_4ln = &waveshare_8_0_a_mode,\n> +\t.mode_2ln = &waveshare_8_0_a_mode,\n> +\t.format = MIPI_DSI_FMT_RGB888,\n> +\t.init = waveshare_8_0_a_init,\n> +\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n> +\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n> +};\n> +\n> +static const struct drm_display_mode waveshare_10_1_a_mode = {\n> +\t.clock\t\t= (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,\n> +\n> +\t.hdisplay\t= 800,\n> +\t.hsync_start\t= 800 + 40,\n> +\t.hsync_end\t= 800 + 40 + 20,\n> +\t.htotal\t\t= 800 + 40 + 20 + 20,\n> +\n> +\t.vdisplay\t= 1280,\n> +\t.vsync_start\t= 1280 + 20,\n> +\t.vsync_end\t= 1280 + 20 + 20,\n> +\t.vtotal\t\t= 1280 + 20 + 20 + 4,\n> +\n> +\t.width_mm\t= 135,\n> +\t.height_mm\t= 216,\n> +\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n> +};\n> +\n> +static int waveshare_10_1_a_init(struct jadard *jadard)\n> +{\n> +\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x00);\n> +\tjadard_enable_standard_cmds(&dsi_ctx);\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n> +\tif (jadard->dsi->lanes == 4)\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3b);\n> +\telse {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x38);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x38);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xaf);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xaf);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0d);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x17);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6b);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5c);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5b);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4f);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4d);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2b);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3d);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x41);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2a);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x44);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x4e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x20);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0f);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x59);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4c);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x48);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x3a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x26);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6b);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5c);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5b);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4f);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4d);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2b);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3d);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x41);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2a);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x63);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x44);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x52);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x4e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0f);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x59);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4c);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x48);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x3a);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x26);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x02);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x17);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x37);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x37);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x42);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x42);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x40);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x5f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x57);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x57);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x77);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x77);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x47);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x47);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x45);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49);\n> +\tif (jadard->dsi->lanes == 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x1e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x1e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x1f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x1f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x1f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x17);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37);\n> +\t} else {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x41);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x41);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x40);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x40);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x5e);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x5f);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x57);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x57);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x77);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x77);\n> +\t}\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x48);\n> +\tif (jadard->dsi->lanes == 4)\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);\n> +\telse\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x08);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x0a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x0a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x06);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x17);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x17);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x37);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x37);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x09);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0b);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);\n> +\tif (jadard->dsi->lanes == 4)\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x16);\n> +\telse\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x34);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x05);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n> +\tif (jadard->dsi->lanes == 4)\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1d);\n> +\telse\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x07);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6a);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xff);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xdd);\n> +\tif (jadard->dsi->lanes == 4)\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3f);\n> +\telse\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2c);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x17);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x14);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x82);\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);\n> +\tif (jadard->dsi->lanes != 4) {\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n> +\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n> +\t}\n> +\n> +\tjd9365da_switch_page(&dsi_ctx, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x0c);\n> +\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n> +\tmsleep(120);\n> +\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n> +\tmsleep(60);\n> +\n> +\treturn dsi_ctx.accum_err;\n> +}\n> +\n> +static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {\n> +\t.mode_4ln = &waveshare_10_1_a_mode,\n> +\t.mode_2ln = &waveshare_10_1_a_mode,\n> +\t.format = MIPI_DSI_FMT_RGB888,\n> +\t.init = waveshare_10_1_a_init,\n> +\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n> +\t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n> +};\n> +\n> static int jadard_dsi_probe(struct mipi_dsi_device *dsi)\n> {\n> \tstruct device *dev = &dsi->dev;\n> @@ -2198,6 +2758,14 @@ static const struct of_device_id jadard_of_match[] = {\n> \t\t.compatible = \"waveshare,4.0-dsi-touch-c\",\n> \t\t.data = &waveshare_4_0_inch_c_desc\n> \t},\n> +\t{\n> +\t\t.compatible = \"waveshare,8.0-dsi-touch-a\",\n> +\t\t.data = &waveshare_8_0_inch_a_desc\n> +\t},\n> +\t{\n> +\t\t.compatible = \"waveshare,10.1-dsi-touch-a\",\n> +\t\t.data = &waveshare_10_1_inch_a_desc\n> +\t},\n> \t{ /* sentinel */ }\n> };\n> MODULE_DEVICE_TABLE(of, jadard_of_match);\n> \n\nReviewed-by: Neil Armstrong \n\nThanks,\nNeil","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=g5fqMHyb;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n 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(PDT)","Message-ID":"<908b1360-e53d-4f33-82ce-4e2b67ddcfb7@linaro.org>","Date":"Tue, 14 Apr 2026 14:58:57 +0200","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","From":"Neil Armstrong ","Reply-To":"Neil Armstrong ","Subject":"Re: [PATCH v3 15/21] drm/panel: jadard-jd9365da-h3: support Waveshare\n WXGA DSI panels","To":"Dmitry Baryshkov ,\n Jessica Zhang , David Airlie ,\n Simona Vetter ,\n Maarten Lankhorst ,\n Maxime Ripard , Thomas Zimmermann ,\n Rob Herring , Krzysztof Kozlowski ,\n Conor Dooley ,\n Cong Yang ,\n Ondrej Jirman , Javier Martinez Canillas ,\n Jagan Teki , Liam Girdwood ,\n Mark Brown , Linus Walleij ,\n Bartosz Golaszewski , Jie Gan ","Cc":"dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,\n Riccardo Mereu ","References":"<20260413-waveshare-dsi-touch-v3-0-3aeb53022c32@oss.qualcomm.com>\n <20260413-waveshare-dsi-touch-v3-15-3aeb53022c32@oss.qualcomm.com>","Content-Language":"en-US, fr","Autocrypt":"addr=neil.armstrong@linaro.org; keydata=\n xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP\n GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4\n BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9\n qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik\n 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB\n AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA\n OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk\n Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04\n YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ\n GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw\n 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<20260413-waveshare-dsi-touch-v3-15-3aeb53022c32@oss.qualcomm.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit"}}]