[{"id":3676431,"web_url":"http://patchwork.ozlabs.org/comment/3676431/","msgid":"<03aff8820f4ae0da6ae00955531beab818b7a942.camel@mediatek.com>","list_archive_url":null,"date":"2026-04-13T03:45:35","subject":"Re: [PATCH] mips: mtmips: align MT7621 image blobs to 8-byte boundary","submitter":{"id":75269,"url":"http://patchwork.ozlabs.org/api/people/75269/","name":"Weijie Gao","email":"weijie.gao@mediatek.com"},"content":"Hi Shiji,\n\nOn Sun, 2026-04-12 at 20:12 +0800, Shiji Yang wrote:\n> \n> MT7621 doesn't boot on u-boot v2026.04. Fix it by correcting the\n> u-boot aligned offset.\n> \n> Fixes: d9e183a04c92 (\"MIPS: Assure end of U-Boot is at 8-byte aligned\n> offset\")\n> Signed-off-by: Shiji Yang \n> ---\n> arch/mips/dts/mt7621-u-boot.dtsi | 8 ++++----\n> 1 file changed, 4 insertions(+), 4 deletions(-)\n\nReviewed-by: Weijie Gao \n\n> \n> diff --git a/arch/mips/dts/mt7621-u-boot.dtsi b/arch/mips/dts/mt7621-\n> u-boot.dtsi\n> index fbac2ade25a..a6e585a0853 100644\n> --- a/arch/mips/dts/mt7621-u-boot.dtsi\n> +++ b/arch/mips/dts/mt7621-u-boot.dtsi\n> @@ -47,13 +47,13 @@\n> \n> &binman {\n> u-boot-spl-ddr {\n> - align = <4>;\n> - align-size = <4>;\n> + align = <8>;\n> + align-size = <8>;\n> filename = \"u-boot-spl-ddr.bin\";\n> pad-byte = <0xff>;\n> \n> u-boot-spl {\n> - align-end = <4>;\n> + align-end = <8>;\n> filename = \"u-boot-spl.bin\";\n> };\n> \n> @@ -90,7 +90,7 @@\n> \n> #ifndef CONFIG_MT7621_BOOT_FROM_NAND\n> u-boot-tpl {\n> - align-end = <4>;\n> + align-end = <8>;\n> filename = \"u-boot-tpl.bin\";\n> };\n> #endif\n> --\n> 2.53.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256\n header.s=dk header.b=OfxwV1N0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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