[{"id":3676667,"web_url":"http://patchwork.ozlabs.org/comment/3676667/","msgid":"<2B283171-55E2-4DC1-9F5F-BE2254E8DB7D@gmail.com>","list_archive_url":null,"date":"2026-04-13T11:30:20","subject":"Re: [PATCH] hw/ppc/e500: fix bus-frequency property hardcoded to zero\n in CPU FDT node","submitter":{"id":83251,"url":"http://patchwork.ozlabs.org/api/people/83251/","name":"Bernhard Beschow","email":"shentey@gmail.com"},"content":"+ qemu-stable\n\nAm 11. April 2026 15:45:35 UTC schrieb Vivien LEGER :\n>The bus-frequency property in the CPU FDT node was hardcoded to 0.\n>This is incorrect - it should reflect the actual platform bus clock\n>frequency, as firmware and RTOSes use it to derive peripheral clock\n>rates.\n>\n>Notably, the RTEMS QorIQ BSP uses bus-frequency to program the MPIC\n>global timer interval. With bus-frequency=0, the timer interval\n>overflows to ~85 seconds, preventing any clock interrupts from firing.\n>\n>Fix by adding a bus_freq field to PPCE500MachineClass and using it in\n>the FDT generator. Set bus_freq = PLATFORM_CLK_FREQ_HZ (400MHz) for\n>existing machines, matching the existing clock_freq value.\n>\n>Signed-off-by: Vivien LEGER \n>---\n> hw/ppc/e500.c | 2 +-\n> hw/ppc/e500.h | 1 +\n> hw/ppc/e500plat.c | 1 +\n> hw/ppc/mpc8544ds.c | 1 +\n> 4 files changed, 4 insertions(+), 1 deletion(-)\n>\n>diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c\n>index d6ca2e8..5be2f20 100644\n>--- a/hw/ppc/e500.c\n>+++ b/hw/ppc/e500.c\n>@@ -518,7 +518,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,\n> env->icache_line_size);\n> qemu_fdt_setprop_cell(fdt, cpu_name, \"d-cache-size\", 0x8000);\n> qemu_fdt_setprop_cell(fdt, cpu_name, \"i-cache-size\", 0x8000);\n>- qemu_fdt_setprop_cell(fdt, cpu_name, \"bus-frequency\", 0);\n>+ qemu_fdt_setprop_cell(fdt, cpu_name, \"bus-frequency\", pmc->bus_freq);\n> if (cpu->cpu_index) {\n> qemu_fdt_setprop_string(fdt, cpu_name, \"status\", \"disabled\");\n> qemu_fdt_setprop_string(fdt, cpu_name, \"enable-method\",\n>diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h\n>index 11f8ae5..6d56c7b 100644\n>--- a/hw/ppc/e500.h\n>+++ b/hw/ppc/e500.h\n>@@ -40,6 +40,7 @@ struct PPCE500MachineClass {\n> hwaddr pci_mmio_bus_base;\n> hwaddr spin_base;\n> uint32_t clock_freq;\n>+ uint32_t bus_freq;\n> uint32_t tb_freq;\n> };\n> \n>diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c\n>index ca56472..85cec81 100644\n>--- a/hw/ppc/e500plat.c\n>+++ b/hw/ppc/e500plat.c\n>@@ -94,6 +94,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, const void *data)\n> pmc->pci_mmio_bus_base = 0xE0000000ULL;\n> pmc->spin_base = 0xFEF000000ULL;\n> pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;\n>+ pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;\n> pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;\n> \n> mc->desc = \"generic paravirt e500 platform\";\n>diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c\n>index 5826985..d022761 100644\n>--- a/hw/ppc/mpc8544ds.c\n>+++ b/hw/ppc/mpc8544ds.c\n>@@ -56,6 +56,7 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, const void *data)\n> pmc->pci_pio_base = 0xE1000000ULL;\n> pmc->spin_base = 0xEF000000ULL;\n> pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;\n>+ pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;\n> pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;\n> \n> mc->desc = \"mpc8544ds\";\n\nReviewed-by: Bernhard Beschow ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=JvX2GB1W;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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