[{"id":3676689,"web_url":"http://patchwork.ozlabs.org/comment/3676689/","msgid":"","date":"2026-04-13T11:59:19","subject":"Re: [PATCH v4 20/24] PCI: Add macros for legacy I/O and memory\n address space sizes","submitter":{"id":83553,"url":"http://patchwork.ozlabs.org/api/people/83553/","name":"Ilpo Järvinen","email":"ilpo.jarvinen@linux.intel.com"},"content":"On Sat, 11 Apr 2026, Krzysztof Wilczyński wrote:\n\n> Add defines for the standard PCI legacy address space sizes,\n> replacing the raw literals used by the legacy sysfs attributes.\n> \n> Suggested-by: Ilpo Järvinen \n> Signed-off-by: Krzysztof Wilczyński \n> ---\n> include/linux/pci.h | 5 +++++\n> 1 file changed, 5 insertions(+)\n> \n> diff --git a/include/linux/pci.h b/include/linux/pci.h\n> index f6f55005f82d..6b630bac8c08 100644\n> --- a/include/linux/pci.h\n> +++ b/include/linux/pci.h\n> @@ -27,6 +27,7 @@\n> #include \n> \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -1167,6 +1168,10 @@ enum {\n> /* These external functions are only available when PCI support is enabled */\n> #ifdef CONFIG_PCI\n> \n> +/* PCI legacy I/O port and memory address space sizes. */\n> +#define PCI_LEGACY_IO_SIZE\t(SZ_64K - 1)\n> +#define PCI_LEGACY_MEM_SIZE\tSZ_1M\n> +\n> extern unsigned int pci_flags;\n> \n> static inline void pci_set_flags(int flags) { pci_flags = flags; }\n> \n\nShouldn't this also convert the use in pci-sysfs.c (which you now mixed \ninto the static attrs conversion patch)?","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=T2Kx19Z1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-19688-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n arc=none smtp.remote-ip=198.175.65.13","lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com","lists.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=T2Kx19Z1;\n\tdkim-atps=neutral","lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=linux.intel.com\n (client-ip=198.175.65.13; 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a=\"88088839\"","E=Sophos;i=\"6.23,177,1770624000\";\n d=\"scan'208\";a=\"88088839\"","E=Sophos;i=\"6.23,177,1770624000\";\n d=\"scan'208\";a=\"226597919\""],"X-ExtLoop1":"1","From":"=?utf-8?q?Ilpo_J=C3=A4rvinen?= ","Date":"Mon, 13 Apr 2026 14:59:19 +0300 (EEST)","To":"=?iso-8859-2?q?Krzysztof_Wilczy=F1ski?= ","cc":"Bjorn Helgaas , Bjorn Helgaas ,\n Manivannan Sadhasivam ,\n Lorenzo Pieralisi ,\n Magnus Lindholm , Matt Turner ,\n Richard Henderson ,\n Christophe Leroy ,\n Madhavan Srinivasan ,\n Michael Ellerman , Nicholas Piggin ,\n Dexuan Cui ,\n =?iso-8859-2?q?Krzysztof_Ha=B3asa?= ,\n Lukas Wunner , Oliver O'Halloran ,\n Saurabh Singh Sengar ,\n Shuan He ,\n Srivatsa Bhat , linux-pci@vger.kernel.org,\n linux-alpha@vger.kernel.org, linuxppc-dev@lists.ozlabs.org","Subject":"Re: [PATCH v4 20/24] PCI: Add macros for legacy I/O and memory\n address space sizes","In-Reply-To":"<20260411080148.471335-21-kwilczynski@kernel.org>","Message-ID":"","References":"<20260411080148.471335-1-kwilczynski@kernel.org>\n <20260411080148.471335-21-kwilczynski@kernel.org>","X-Mailing-List":"linuxppc-dev@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Archive":",\n ","List-Subscribe":",\n ,\n ","List-Unsubscribe":"","Precedence":"list","MIME-Version":"1.0","Content-Type":"multipart/mixed; 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