[{"id":3676107,"web_url":"http://patchwork.ozlabs.org/comment/3676107/","msgid":"","list_archive_url":null,"date":"2026-04-09T07:44:43","subject":"Re: [PATCH 1/2] dt-bindings: rtc: nct3018y: add nuvoton,ctrl-reg-val\n property","submitter":{"id":85937,"url":"http://patchwork.ozlabs.org/api/people/85937/","name":"David Wang","email":"tomato1220@gmail.com"},"content":"On Apr 9, 2026, at 15:23, Krzysztof Kozlowski wrote:\n>\n> On 09/04/2026 09:21, David Wang wrote:\n> > Add \"nuvoton,ctrl-reg-val\" vendor property to allow optional\n> > initialization of the RTC control register (0x0A).\n> >\n> > This allows platform-specific configurations like 24h mode and\n> > write ownership to be defined via Device Tree.\n> >\n> > Signed-off-by: David Wang \n> > ---\n> > Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml | 5 +++++\n> > 1 file changed, 5 insertions(+)\n> >\n> > diff --git a/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml b/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml\n> > index 4f9b5604acd9..0984dfb77170 100644\n> > --- a/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml\n> > +++ b/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml\n> > @@ -24,6 +24,10 @@ properties:\n> >\n> > reset-source: true\n> >\n> > + nuvoton,ctrl-reg-val:\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + description: Initial value for the control register (0x0A).\n>\n> 24h mode is not a property of a board. I don't know what \"write\n> ownership\" is.\n>\n> Best regards,\n> Krzysztof\n\nHi Krzysztof,\n\nThanks for your feedback. Let me clarify these two points based on the\nNCT3018Y datasheet:\n1. Regarding \"write ownership\": The NCT3018Y features two I2C\ninterfaces (Primary and Secondary). The TWO (Time Write Ownership) bit\nin the control register determines which interface has the authority\nto write to the RTC. We need to ensure the interface connected to our\nSoC is granted this ownership during probe—especially for factory-new\nchips—to ensure the RTC is writable.\n2. Regarding \"24h mode\": This bit determines the internal data format\nin which time is stored within the RTC hardware. Setting this ensures\nthe hardware's internal storage layout matches the driver's\nexpectation from the start.\n\nBest regards,\nDavid Wang","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=a9/FfOpA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; helo=lists.ozlabs.org;\n envelope-from=openbmc+bounces-1799-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n arc=pass smtp.remote-ip=\"2607:f8b0:4864:20::729\" arc.chain=google.com","lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","lists.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=a9/FfOpA;\n\tdkim-atps=neutral","lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com\n (client-ip=2607:f8b0:4864:20::729; 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Thu, 09 Apr 2026\n 00:44:15 -0700 (PDT)","X-Mailing-List":"openbmc@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Subscribe":",\n ,\n ","List-Unsubscribe":"","Precedence":"list","MIME-Version":"1.0","References":"\n \n ","In-Reply-To":"","From":"David Wang ","Date":"Thu, 9 Apr 2026 15:44:43 +0800","X-Gm-Features":"AQROBzCF7F3D8qQZzH4nVF7DtpNul6eHMhQM5j4hlrJJj6BRCmL9I0ox9rpAVNY","Message-ID":"\n ","Subject":"Re: [PATCH 1/2] dt-bindings: rtc: nct3018y: add nuvoton,ctrl-reg-val\n property","To":"Krzysztof Kozlowski ","Cc":"a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh@kernel.org,\n\tkrzk+dt@kernel.org, conor+dt@kernel.org, andrew@aj.id.au,\n\tavi.fishman@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com,\n\tventure@google.com, yuenn@google.com, benjaminfair@google.com,\n\tctcchien@nuvoton.com, mimi05633@gmail.com, openbmc@lists.ozlabs.org,\n\tlinux-rtc@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, davidwang@quantatw.com","Content-Type":"text/plain; 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