[{"id":3676372,"web_url":"http://patchwork.ozlabs.org/comment/3676372/","msgid":"<CH3PR12MB75480CBCF41ECBA8BFB983CDAB272@CH3PR12MB7548.namprd12.prod.outlook.com>","list_archive_url":null,"date":"2026-04-12T20:28:14","subject":"RE: [PATCH v2 2/2] hw/arm/smmuv3: Avoid including CONFIG_DEVICES in\n hw/ header","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/people/91580/","name":"Shameer Kolothum Thodi","email":"skolothumtho@nvidia.com"},"content":"> -----Original Message-----\n> From: Philippe Mathieu-Daudé <philmd@linaro.org>\n> Sent: 10 April 2026 21:01\n> To: qemu-devel@nongnu.org\n> Cc: Nathan Chen <nathanc@nvidia.com>; qemu-arm@nongnu.org; Peter\n> Maydell <peter.maydell@linaro.org>; Shameer Kolothum Thodi\n> <skolothumtho@nvidia.com>; Eric Auger <eric.auger@redhat.com>; Philippe\n> Mathieu-Daudé <philmd@linaro.org>; Thomas Huth <thuth@redhat.com>\n> Subject: [PATCH v2 2/2] hw/arm/smmuv3: Avoid including CONFIG_DEVICES\n> in hw/ header\n> \n> External email: Use caution opening links or attachments\n> \n> \n> By turning the inline functions into stubs we can avoid the\n> use of target-specific CONFIG_DEVICES include in a hw/ header,\n> allowing to build the source files including it as common objects.\n> \n> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n> Reviewed-by: Thomas Huth <thuth@redhat.com>\n\nReviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>\n\nThanks,\nShameer\n\n>  hw/arm/smmuv3-accel.h       | 42 ------------------------------\n>  hw/arm/smmuv3-accel-stubs.c | 52\n> +++++++++++++++++++++++++++++++++++++\n>  hw/arm/meson.build          |  5 ++--\n>  3 files changed, 55 insertions(+), 44 deletions(-)\n>  create mode 100644 hw/arm/smmuv3-accel-stubs.c\n> \n> diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\n> index 1ca2c80a933..85669d0e00e 100644\n> --- a/hw/arm/smmuv3-accel.h\n> +++ b/hw/arm/smmuv3-accel.h\n> @@ -14,7 +14,6 @@\n>  #ifdef CONFIG_LINUX\n>  #include <linux/iommufd.h>\n>  #endif\n> -#include CONFIG_DEVICES\n> \n>  /*\n>   * Represents an accelerated SMMU instance backed by an iommufd vIOMMU\n> object.\n> @@ -41,7 +40,6 @@ typedef struct SMMUv3AccelDevice {\n>      SMMUv3AccelState *s_accel;\n>  } SMMUv3AccelDevice;\n> \n> -#ifdef CONFIG_ARM_SMMUV3_ACCEL\n>  bool smmuv3_accel_init(SMMUv3State *s, Error **errp);\n>  bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int\n> sid,\n>                                Error **errp);\n> @@ -53,45 +51,5 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s,\n> void *cmd, SMMUDevice *sdev,\n>  void smmuv3_accel_idr_override(SMMUv3State *s);\n>  bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n>  void smmuv3_accel_reset(SMMUv3State *s);\n> -#else\n> -#include \"qapi/error.h\"\n> -static inline bool smmuv3_accel_init(SMMUv3State *s, Error **errp)\n> -{\n> -    error_setg(errp, \"accel=on support not compiled in\");\n> -    return false;\n> -}\n> -static inline bool\n> -smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid,\n> -                         Error **errp)\n> -{\n> -    return true;\n> -}\n> -static inline bool\n> -smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange *range,\n> -                               Error **errp)\n> -{\n> -    return true;\n> -}\n> -static inline bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error\n> **errp)\n> -{\n> -    return true;\n> -}\n> -static inline bool\n> -smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice\n> *sdev,\n> -                           Error **errp)\n> -{\n> -    return true;\n> -}\n> -static inline void smmuv3_accel_idr_override(SMMUv3State *s)\n> -{\n> -}\n> -static inline bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error\n> **errp)\n> -{\n> -    return true;\n> -}\n> -static inline void smmuv3_accel_reset(SMMUv3State *s)\n> -{\n> -}\n> -#endif\n> \n>  #endif /* HW_ARM_SMMUV3_ACCEL_H */\n> diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c\n> new file mode 100644\n> index 00000000000..70cef66966a\n> --- /dev/null\n> +++ b/hw/arm/smmuv3-accel-stubs.c\n> @@ -0,0 +1,52 @@\n> +/*\n> + * Stubs for accelerated SMMU instance backed by an iommufd vIOMMU\n> object.\n> + *\n> + * SPDX-License-Identifier: GPL-2.0-or-later\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"qapi/error.h\"\n> +#include \"hw/arm/smmuv3.h\"\n> +#include \"hw/arm/smmuv3-accel.h\"\n> +\n> +bool smmuv3_accel_init(SMMUv3State *s, Error **errp)\n> +{\n> +    error_setg(errp, \"accel=on support not compiled in\");\n> +    return false;\n> +}\n> +\n> +bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int\n> sid,\n> +                              Error **errp)\n> +{\n> +    return true;\n> +}\n> +\n> +bool smmuv3_accel_install_ste_range(SMMUv3State *s, SMMUSIDRange\n> *range,\n> +                                    Error **errp)\n> +{\n> +    return true;\n> +}\n> +\n> +bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp)\n> +{\n> +    return true;\n> +}\n> +\n> +bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd,\n> SMMUDevice *sdev,\n> +                                Error **errp)\n> +{\n> +    return true;\n> +}\n> +\n> +void smmuv3_accel_idr_override(SMMUv3State *s)\n> +{\n> +}\n> +\n> +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n> +{\n> +    return true;\n> +}\n> +\n> +void smmuv3_accel_reset(SMMUv3State *s)\n> +{\n> +}\n> diff --git a/hw/arm/meson.build b/hw/arm/meson.build\n> index b187b946f04..3be1252c4f1 100644\n> --- a/hw/arm/meson.build\n> +++ b/hw/arm/meson.build\n> @@ -84,8 +84,9 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE',\n> if_true: files('armsse.c'))\n>  arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c',\n> 'mcimx7d-sabre.c'))\n>  arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-\n> imx8mp.c'))\n>  arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true:\n> files('imx8mp-evk.c'))\n> -arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))\n> -arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-\n> accel.c'))\n> +arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true:\n> files('smmuv3.c'))\n> +arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true:\n> files('smmuv3-accel.c'))\n> +stub_ss.add(files('smmuv3-accel-stubs.c'))\n>  arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-\n> imx6ul.c', 'mcimx6ul-evk.c'))\n>  arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true:\n> files('nrf51_soc.c'))\n>  arm_common_ss.add(when: 'CONFIG_XEN', if_true: files(\n> --\n> 2.53.0","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Zp/Ux3Y9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fv2F01TZVz1yGj\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 13 Apr 2026 06:28:50 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wC1Pr-00043M-Eg; Sun, 12 Apr 2026 16:28:23 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <skolothumtho@nvidia.com>)\n id 1wC1Po-000401-7k; Sun, 12 Apr 2026 16:28:20 -0400","from\n mail-southcentralusazlp170120001.outbound.protection.outlook.com\n ([2a01:111:f403:c10d::1] helo=SN4PR2101CU001.outbound.protection.outlook.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <skolothumtho@nvidia.com>)\n id 1wC1Pm-0007T0-FT; Sun, 12 Apr 2026 16:28:19 -0400","from CH3PR12MB7548.namprd12.prod.outlook.com (2603:10b6:610:144::12)\n by CY5PR12MB6202.namprd12.prod.outlook.com (2603:10b6:930:25::8) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.20; Sun, 12 Apr\n 2026 20:28:14 +0000","from CH3PR12MB7548.namprd12.prod.outlook.com\n ([fe80::b710:d6a1:ab16:76de]) by CH3PR12MB7548.namprd12.prod.outlook.com\n ([fe80::b710:d6a1:ab16:76de%6]) with mapi id 15.20.9818.017; Sun, 12 Apr 2026\n 20:28:14 +0000"],"ARC-Seal":"i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=sCN5545vqunWjvAO5CSap/PtGRJQ0YM2kdxpkMtDOcrbOiLw1kYNkTEY9+oyQ5L11BJE/D7pjiyaD0pnTKucU/eaWxYl+6WeejRjzCPxXwj0qiyatUP0E/QNhP2VgKyr4vaFuyYlvmtgjU0NuyrV1QclIqDUK/UtR3ww5EMnB5xZk2iLAP50gDB4uLlM+E7f41x3Nr6Q2yKTH5idh2LOAJSSDICXJWtsEyQM/8kQQARaocavRFCt46IigTz9pHlAM+yZkt4/PE9NxhLBbKEJEcmDGn8tDVedCw/vNXjrAGoYVrVZC937xHK4B7rK09NZ4Jq4RkMcnBhHmhQI/sufQQ==","ARC-Message-Signature":"i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=faZ2VG+ByQ997MfXCAVPef5/mkUkBOV1HnpA+LeBNGk=;\n b=gMDEHLC7H4j+2Iv6rnzkspp7+OmZ1fdl74YY421OKLA9Kft8i5l/aBf5+rudN20QiX+TAy/GuUqjk4zlkMLlcWfWqZL0/S4JmrHkkeeoJhdH1ZzSVZlpwLhtPqezWECtfWqkvOWb+10h+PWRygOA5wjOOtqHc4+qLlhqjnIDUX/PqZAsvuyQ/xyaN9TYzy+PVqIZFvx9glK/IJjCd12Foc7ZPB27dJi+gO1tTgbP6hSQWeayA3KAy0/9zUvJFlGIfDb6s9CR9yaBQ+wX/g5O3Af2PxYKKE4chcCU79/PdjKGaQzQZX8+8lCuTHe1td2Yb11ufAsxz4hU11KaLZCEXA==","ARC-Authentication-Results":"i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=faZ2VG+ByQ997MfXCAVPef5/mkUkBOV1HnpA+LeBNGk=;\n b=Zp/Ux3Y9hqntFuO6LgrL6gAzfbGXAN0jgak2jKt2wyovTvp13CDDjW7/4S1yOzySGCI5WpsyHmrbJmaMxWS7q+xSpft7zszE7ssNgm3CjHKvKRvn/DZi6JfFOTPE6P5k9NudFY3496lo+ddX9N3whs4u7UCJKZnhoAekAfgHPQtznZBE96/nJ4IXjoteUHU2rts9ssxaSGFIj4VXGjsAmB0CfMzfm3GZdQSqspBU5DFK4ORvrfThV2DitybVM5pKa+Vfbbdr5OowwUNoX15S0yXlJHSCnq05gFHVVKF+Erniqvw4AkeO4GNqIUqSX7LWIe7pvfvruC6YwuurQma9Sw==","From":"Shameer Kolothum Thodi <skolothumtho@nvidia.com>","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n \"qemu-devel@nongnu.org\" <qemu-devel@nongnu.org>","CC":"Nathan Chen <nathanc@nvidia.com>, \"qemu-arm@nongnu.org\"\n <qemu-arm@nongnu.org>, Peter Maydell <peter.maydell@linaro.org>, Eric Auger\n <eric.auger@redhat.com>, Thomas Huth <thuth@redhat.com>","Subject":"RE: [PATCH v2 2/2] hw/arm/smmuv3: Avoid including CONFIG_DEVICES in\n hw/ header","Thread-Topic":"[PATCH v2 2/2] hw/arm/smmuv3: Avoid including CONFIG_DEVICES in\n hw/ header","Thread-Index":"AQHcySS/gKVkLmsPIUqm6+CGbsWleLXb42GQ","Date":"Sun, 12 Apr 2026 20:28:14 +0000","Message-ID":"\n <CH3PR12MB75480CBCF41ECBA8BFB983CDAB272@CH3PR12MB7548.namprd12.prod.outlook.com>","References":"<20260410200031.18572-1-philmd@linaro.org>\n <20260410200031.18572-3-philmd@linaro.org>","In-Reply-To":"<20260410200031.18572-3-philmd@linaro.org>","Accept-Language":"en-US, en-GB","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Zp/Ux3Y9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"],"x-ms-publictraffictype":"Email","x-ms-traffictypediagnostic":"CH3PR12MB7548:EE_|CY5PR12MB6202:EE_","x-ms-office365-filtering-correlation-id":"92c0710e-2711-4ac4-2e8d-08de98d205cf","x-ms-exchange-senderadcheck":"1","x-ms-exchange-antispam-relay":"0","x-microsoft-antispam":"BCL:0;\n ARA:13230040|376014|366016|1800799024|38070700021|22082099003|56012099003|18002099003;","x-microsoft-antispam-message-info":"\n +i1M/je1SbQB56GnJowGZgmc4h1ujtJIxIXaJyJLkrhfRp6lpMSMSu/Zzc6j48KozxZJYhJa/OAOQP+Z+0zPOofKlBG4YlXRLup+ZvcEpBXIWp51Dwcl0LAoFQNQoQKBwmJE1ySiQ3BrAukH+rTSMZC3l39lIpfHzGW9K9YFeACVS5DaLCCBuNXwrY5+Zqn17VgPBnieKB3R36JujSr3pvzPo8jPJ0xujAKvs0Otn63tiPQdpFor3CHb+NGgfKv+dv2+hUxR0c20ugX42StRr2hVrdyFL/mPPcM1dPgj7kw/EuplmzmOh29PgcM4pOGFe1ZS9alL9pWBTLAQuY/0kTs1iRmbZxjjnaCV70Wtc3XCLjGtw0v5FH3T6irk0iJbzRgdB1Bs5woLwBNlcWYGGv5TvjmcqeoqOjzz6mWxZqVSkWjxrmKBYWt7Ui3gM1M/BMjsovXNQxaQVE1AIb2rrMB3B1mPvqdT8ZaIMJ88ZnIXBTXnwJTSmg5CL4SbBfW5IPlJrneucCvnnVbhb1+QL8dgzNKJ12f3mNFR90NW9jdBciP7bFpSm8V2ItdeGqE8tkl0Qy86GaN61kme58e2vdaRQ31aclnupy5HI2z8Hw6QML/94d53BMm0iPc0+dmkYIJppBpuHjU5k72ViqHO8pJHOr1DQlwME29jLyEaWavEqrxckMTQwhiXPlnZ1InJ4wWYoGIufM2/h3n/iVI5BpYYPm/lIs5tZUNt14WI+0P02lQXLGa49PAqr829Ro6wcYRiZPJxmxrl8kqKvnhQ0v5qCL/Ws44b8+CrIhb+s5M=","x-forefront-antispam-report":"CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:CH3PR12MB7548.namprd12.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230040)(376014)(366016)(1800799024)(38070700021)(22082099003)(56012099003)(18002099003);\n DIR:OUT; SFP:1101;","x-ms-exchange-antispam-messagedata-chunkcount":"1","x-ms-exchange-antispam-messagedata-0":"=?utf-8?q?agT39Wr8EpEhl7N32mROy9GjdRpU?=\n\t=?utf-8?q?6ANpCjtWMv70JSS6vKz/QRkGolLvls36GvS+1E21dWS/EWmqtYf7Ic6D0i1180lF+?=\n\t=?utf-8?q?fxXzb3bifZaSlt/k2JpyABJyPMTNFjicXtvFVp0XHum7Ze9yOw+C9P+7SfUgSSR73?=\n\t=?utf-8?q?DM8AjoeaF78nhbp7+ZjXdf2zKfYsb+RWozXjZ9MkJ/yKcVkIGqU8f0E1RxF/2Ugqv?=\n\t=?utf-8?q?3NGzxs7cj/nN7gBUK3Stlj/Bq1RjgWl5cMUU0wcchCc0sPz8/yvajjLCJRp+7zxwc?=\n\t=?utf-8?q?GwxmSI2O3+0BDX44FyVP75SF/EnM+sQSOieCnSSkeURT4iDhEaoEne8F89UG0sEz1?=\n\t=?utf-8?q?eB0hjDIrnHUFiyL9E3lR5g3H2QY2XOCNtobLpkmInbWzvu161By2gXosgkmsCyPRH?=\n\t=?utf-8?q?ycaAIzMsjxi9zQw73fx8L5FuQI6YVLhPFGmUSYrOG4u5s3dB5u/ojEBiBUt4IRN1y?=\n\t=?utf-8?q?SYElDrKpHgitQR/3WeHd6cWuDxY4ZGXu6W435UdZJdwZiP7uBqA1IMmlCppl7JK2A?=\n\t=?utf-8?q?pdS17KIJiSZOgRysOkfnQRkCkiuP4dqRJ79RvjvJ87v5zkY54gOVlGLga7zEgNTN/?=\n\t=?utf-8?q?2gowWqO99RmZ1Ye+irQNRUEHkFD1r5FXPwtASzsvF1klB5+20rLLgJOXC6oWTx8Z9?=\n\t=?utf-8?q?RLhJUbx9KEHx6waL9pDRfqsfZxOF57YAgo8vH+2tBGIIGfsVX7sY9kNAJVJW5tOPV?=\n\t=?utf-8?q?0XoioZZZooK1yenm6WYBNBn7bEgRFwkf45MdxlzxXHrj3Vc99xqUf0A4Vf93tBg/X?=\n\t=?utf-8?q?EVrA9SFQxDzfRT4aOLLcXvRSOvnKTlwjRobORBADq0apAhUOFgsW4a3cvhy5UhMBN?=\n\t=?utf-8?q?dJhF/AMz/BX3cUjytonfRiIVEUcOd9x4ympGSW9nfya0o6RC16jAu02trdzY+tQxD?=\n\t=?utf-8?q?BFwK1CPgOw3Wr6dq8oFEqq+a5aXMEzHt3hOgPck5+FI5PNwdxO4EbMxme1Hsa2VH3?=\n\t=?utf-8?q?UEEWi1y/DFDkcZETycrnTaxAoOipJkxQWaIxgr/2I4zynMwciYBix9i0dAonymxD6?=\n\t=?utf-8?q?HusNbaTD+A+S6MoA+gOkJ+S8Vk3qlTJLXTCM4gmeqyQO781KxQ3gBHNzKsvg3DcdN?=\n\t=?utf-8?q?dMEBmFDiydHV7dGSLgP7l44+QIg1geE3VazBLvM0OFyjpZnTwu+kq7Agibcb7tciL?=\n\t=?utf-8?q?wt8UZP3c6zDVY3qLle24moa68BJdKsWAFeeYDgEzFOO2jNPiSp+ZeQTopVw9w4rmR?=\n\t=?utf-8?q?prsexJKsQuxMiIv6R0BHLUQCNJCGp8yonv80Bq6yOBEXqNkIuw7zrk/XnjOyD/PlV?=\n\t=?utf-8?q?MD+4PH6Qu2v9zQrV3uqNrLW25W3BBAngYAL0AGnQVE/Yg1ESZ/GnNmFhV/fr2idah?=\n\t=?utf-8?q?uEWNSNBuZufCcJZ4PeYlq7eTlmF7FomPvd3eHCOURRX6yk0Ba0qSrn6cUxGvp7pks?=\n\t=?utf-8?q?ZIdJYX5toBU2C3tP4GeHnmSFaxpi+iIVU6TuJs9Wr+eHQn58UNHMG9Pxcv8Z0dTrN?=\n\t=?utf-8?q?EIk9PweI9z+2G5tg1p5cQirNsGb7YnWy5Roqj4XNPVoJPLbHZew6XMF4k8eVw4R7k?=\n\t=?utf-8?q?bqigai8aeHc+QXMwZb6AyFYt9z/VyBJFWMgMeu48eguUoDZzWqdM/sqwbQgtZTfz8?=\n\t=?utf-8?q?bjGQsYKDbZnRknZ5LYhPUTO9s1k3mjdlXGFiJo3iajmtA44r4/Vf3x3ksqDI516X+?=\n\t=?utf-8?q?DNPu54f1V0cCU9VL7ji6NugL07gi4cww=3D=3D?=","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"CH3PR12MB7548.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 92c0710e-2711-4ac4-2e8d-08de98d205cf","X-MS-Exchange-CrossTenant-originalarrivaltime":"12 Apr 2026 20:28:14.1158 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n Dy5umLkYTYwT8I1qtu5MAA+xW2fxUZN3P7dQg+p427YiwObAcEfpyljcQGsQ2HNBP2LT4x5fb3wfjdNTKA99Mw==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY5PR12MB6202","Received-SPF":"permerror client-ip=2a01:111:f403:c10d::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=SN4PR2101CU001.outbound.protection.outlook.com","X-Spam_score_int":"-15","X-Spam_score":"-1.6","X-Spam_bar":"-","X-Spam_report":"(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]