[{"id":3676599,"web_url":"http://patchwork.ozlabs.org/comment/3676599/","msgid":"<331159fe-8596-e406-32d5-c9c8c2ad6f8b@loongson.cn>","list_archive_url":null,"date":"2026-04-13T09:32:03","subject":"Re: [PATCH v2] target/loongarch: Add support for dbar hint variants","submitter":{"id":78914,"url":"http://patchwork.ozlabs.org/api/people/78914/","name":"Bibo Mao","email":"maobibo@loongson.cn"},"content":"On 2026/4/10 上午11:37, Song Gao wrote:\n> LoongArch architecture (since LA664) introduces fine-grained dbar\n> hints that allow controlling which memory accesses are ordered by\n> the barrier. Previously, all dbar instructions were treated as a\n> full barrier (TCG_MO_ALL | TCG_BAR_SC).\n> \n> This patch adds support for decoding dbar hints and emitting the\n> appropriate TCG memory barrier flags. For CPUs that do not advertise\n> the DBAR_HINTS feature (cpucfg3.DBAR_HINTS = 0), all dbar hints\n> fall back to a full barrier, preserving compatibility.\n> \n> The hint encoding follows the LoongArch v1.10 specification:\n> * Bit3: barrier for previous read (0: true, 1: false)\n> * Bit2: barrier for previous write (0: true, 1: false)\n> * Bit1: barrier for succeeding read (0: true, 1: false)\n> * Bit0: barrier for succeeding write (0: true, 1: false)\n> \n> The mapping to TCG memory order flags is as follows:\n> TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_LD_ST;\n> TCG_BAR_SC |TCG_MO_ST_LD | TCG_MO_ST_ST;\n> TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_ST_LD;\n> TCG_BAR_SC |TCG_MO_ST_ST | TCG_MO_LD_ST;\n> \n> Special hint handling:\n> - hint 0x700: LL/SC loop barrier, treated as a full barrier as recommended.\n> - hint 0xf and 0x1f: reserved/no-op, treated as no operation\n> \n> Signed-off-by: Song Gao \n> ---\n> target/loongarch/cpu.c | 4 ++\n> .../tcg/insn_trans/trans_memory.c.inc | 62 ++++++++++++++++++-\n> target/loongarch/tcg/translate.c | 1 +\n> target/loongarch/translate.h | 3 +\n> 4 files changed, 68 insertions(+), 2 deletions(-)\n> \n> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\n> index e22568c84a..d8d106b07e 100644\n> --- a/target/loongarch/cpu.c\n> +++ b/target/loongarch/cpu.c\n> @@ -455,6 +455,10 @@ static void loongarch_max_initfn(Object *obj)\n> data = FIELD_DP32(data, CPUCFG2, LLACQ_SCREL, 1);\n> data = FIELD_DP32(data, CPUCFG2, SCQ, 1);\n> cpu->env.cpucfg[2] = data;\n> +\n> + data = cpu->env.cpucfg[3];\n> + data = FIELD_DP32(data, CPUCFG3, DBAR_HINTS, 1);\n> + cpu->env.cpucfg[3] = data;\n> }\n> }\n> \n> diff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n> index e287d46363..e1146fe9ec 100644\n> --- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n> +++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n> @@ -137,11 +137,69 @@ static bool trans_preldx(DisasContext *ctx, arg_preldx * a)\n> return true;\n> }\n> \n> +/*\n> + * Decode dbar hint and emit appropriate TCG memory barrier.\n> + *\n> + * The hint is a 5-bit field (0-31) encoded in the instruction.\n> + * For hint 0x700 (special LL/SC loop barrier), treat as full barrier.\n> + *\n> + * See LoongArch Reference Manual v1.10, Section 4.2.2 for details.\n> + */\n> static bool trans_dbar(DisasContext *ctx, arg_dbar * a)\n> {\n> - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);\n> + int hint = a->imm;\n> + TCGBar bar_flags = 0;\n> +\n> + /* Reserved/no-op hints: 0xf and 0x1f */\n> + if (hint == 0xf || hint == 0x1f) {\n> + return true;\n> + }\n> +\n> + /* If the CPU does not support fine-grained hints,or for the special LL/SC\n> + * loop barrier (0x700), emit a full barrier.\n> + */\n> + if (!avail_DBAR_HINT(ctx) || hint == 0x700) {\n> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n> + return true;\n> + }\n> +\n> + /*\n> + * Fine-grained hint decoding:\n> + * Bits 3-0 control which accesses must be ordered.\n> + * Bit3: barrier for previous read (0: true, 1: false)\n> + * Bit2: barrier for previous write (0: true, 1: false)\n> + * Bit1: barrier for succeeding read (0: true, 1: false)\n> + * Bit0: barrier for succeeding write (0: true, 1: false)\nHi Song,\n\nThis is much better than before, I think it will be better if some \ncomments for BIT4 is added here showing it is discarded here.\n> + *\n> + * For each combination, we set the corresponding TCG_MO_* flag if both\n> + * sides of the barrier require ordering.\n> + */\n> +\n> + bool prev_rd = !(hint & 0x08); /* bit3 */\n> + bool prev_wr = !(hint & 0x04); /* bit2 */\n> + bool succ_rd = !(hint & 0x02); /* bit1 */\n> + bool succ_wr = !(hint & 0x01); /* bit0 */\n> +\n> + if (prev_rd) {\n> + bar_flags |= TCG_MO_LD_LD | TCG_MO_LD_ST;\n> + }\n> + if (prev_wr) {\n> + bar_flags |= TCG_MO_ST_LD | TCG_MO_ST_ST;\n> + }\n> + if (succ_rd) {\n> + bar_flags |= TCG_MO_LD_LD | TCG_MO_ST_LD;\n> + }\n> + if (succ_wr) {\n> + bar_flags |= TCG_MO_ST_ST | TCG_MO_LD_ST;\n> + }\nPreviously I hear that TCG_MO_LD_ST should be default enabled on \nLoongArch, but I am not sure. Is that correct?\n\nThe others looks good to me.\n\nRegards\nBibo Mao\n\n> +\n> + if (bar_flags == 0) {\n> + bar_flags = TCG_MO_ALL;\n> + }\n> +\n> + tcg_gen_mb(bar_flags | TCG_BAR_SC);\n> return true;\n> -}\n> + }\n> \n> static bool trans_ibar(DisasContext *ctx, arg_ibar *a)\n> {\n> diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c\n> index b9ed13d19c..49280b1dd3 100644\n> --- a/target/loongarch/tcg/translate.c\n> +++ b/target/loongarch/tcg/translate.c\n> @@ -149,6 +149,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n> \n> ctx->cpucfg1 = env->cpucfg[1];\n> ctx->cpucfg2 = env->cpucfg[2];\n> + ctx->cpucfg3 = env->cpucfg[3];\n> }\n> \n> static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)\n> diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\n> index ba1c89e57b..8aa8325dc6 100644\n> --- a/target/loongarch/translate.h\n> +++ b/target/loongarch/translate.h\n> @@ -43,6 +43,8 @@\n> #define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_SCREL))\n> #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))\n> \n> +#define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, DBAR_HINTS))\n> +\n> /*\n> * If an operation is being performed on less than TARGET_LONG_BITS,\n> * it may require the inputs to be sign- or zero-extended; which will\n> @@ -66,6 +68,7 @@ typedef struct DisasContext {\n> bool va32; /* 32-bit virtual address */\n> uint32_t cpucfg1;\n> uint32_t cpucfg2;\n> + uint32_t cpucfg3;\n> } DisasContext;\n> \n> void generate_exception(DisasContext *ctx, int excp);\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvMhS6fL6z1yDF\n\tfor ; Mon, 13 Apr 2026 19:35:20 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCDhI-00087Y-6G; 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Linux loongarch64; rv:68.0) Gecko/20100101\n Thunderbird/68.7.0","MIME-Version":"1.0","In-Reply-To":"<20260410033723.1225983-1-gaosong@loongson.cn>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"qMiowJCxPMK8uNxpmwlsAA--.7100S3","X-CM-SenderInfo":"xpdruxter6z05rqj20fqof0/","X-Coremail-Antispam":"1Uk129KBj93XoWxuw1xWw15Ar1DAw45ur48AFc_yoW7Kw45pF\n 4xCF1akFWjqF97Zan7XayYvrn8Zr4xKw42vay3trWfursxWr1kZF1kK3y5KF4xGw4qqF10\n vFWvyw43Wa9IqabCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa\n sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU\n 0xBIdaVrnRJUUUvIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2\n IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v\n e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI\n 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK\n xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx\n 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv\n 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07\n AlzVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02\n F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw\n 1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7Cj\n xVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r\n 4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07Ui\n iSdUUUUU=","Received-SPF":"pass client-ip=114.242.206.163;\n envelope-from=maobibo@loongson.cn;\n helo=mail.loongson.cn","X-Spam_score_int":"-49","X-Spam_score":"-5.0","X-Spam_bar":"-----","X-Spam_report":"(-5.0 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-3.135,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3677008,"web_url":"http://patchwork.ozlabs.org/comment/3677008/","msgid":"","list_archive_url":null,"date":"2026-04-14T02:50:49","subject":"Re: [PATCH v2] target/loongarch: Add support for dbar hint variants","submitter":{"id":82024,"url":"http://patchwork.ozlabs.org/api/people/82024/","name":"gaosong","email":"gaosong@loongson.cn"},"content":"在 2026/4/13 下午5:32, Bibo Mao 写道:\n>\n>\n> On 2026/4/10 上午11:37, Song Gao wrote:\n>> LoongArch architecture (since LA664) introduces fine-grained dbar\n>> hints that allow controlling which memory accesses are ordered by\n>> the barrier. Previously, all dbar instructions were treated as a\n>> full barrier (TCG_MO_ALL | TCG_BAR_SC).\n>>\n>> This patch adds support for decoding dbar hints and emitting the\n>> appropriate TCG memory barrier flags. For CPUs that do not advertise\n>> the DBAR_HINTS feature (cpucfg3.DBAR_HINTS = 0), all dbar hints\n>> fall back to a full barrier, preserving compatibility.\n>>\n>> The hint encoding follows the LoongArch v1.10 specification:\n>>   * Bit3: barrier for previous read (0: true, 1: false)\n>>   * Bit2: barrier for previous write (0: true, 1: false)\n>>   * Bit1: barrier for succeeding read (0: true, 1: false)\n>>   * Bit0: barrier for succeeding write (0: true, 1: false)\n>>\n>> The mapping to TCG memory order flags is as follows:\n>>    TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_LD_ST;\n>>    TCG_BAR_SC |TCG_MO_ST_LD | TCG_MO_ST_ST;\n>>    TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_ST_LD;\n>>    TCG_BAR_SC |TCG_MO_ST_ST | TCG_MO_LD_ST;\n>>\n>> Special hint handling:\n>> - hint 0x700: LL/SC loop barrier, treated as a full barrier as \n>> recommended.\n>> - hint 0xf and 0x1f: reserved/no-op, treated as no operation\n>>\n>> Signed-off-by: Song Gao \n>> ---\n>>   target/loongarch/cpu.c                        |  4 ++\n>>   .../tcg/insn_trans/trans_memory.c.inc         | 62 ++++++++++++++++++-\n>>   target/loongarch/tcg/translate.c              |  1 +\n>>   target/loongarch/translate.h                  |  3 +\n>>   4 files changed, 68 insertions(+), 2 deletions(-)\n>>\n>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\n>> index e22568c84a..d8d106b07e 100644\n>> --- a/target/loongarch/cpu.c\n>> +++ b/target/loongarch/cpu.c\n>> @@ -455,6 +455,10 @@ static void loongarch_max_initfn(Object *obj)\n>>           data = FIELD_DP32(data, CPUCFG2, LLACQ_SCREL, 1);\n>>           data = FIELD_DP32(data, CPUCFG2, SCQ, 1);\n>>           cpu->env.cpucfg[2] = data;\n>> +\n>> +        data = cpu->env.cpucfg[3];\n>> +        data = FIELD_DP32(data, CPUCFG3, DBAR_HINTS, 1);\n>> +        cpu->env.cpucfg[3] = data;\n>>       }\n>>   }\n>>   diff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc \n>> b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n>> index e287d46363..e1146fe9ec 100644\n>> --- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n>> +++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n>> @@ -137,11 +137,69 @@ static bool trans_preldx(DisasContext *ctx, \n>> arg_preldx * a)\n>>       return true;\n>>   }\n>>   +/*\n>> + * Decode dbar hint and emit appropriate TCG memory barrier.\n>> + *\n>> + * The hint is a 5-bit field (0-31) encoded in the instruction.\n>> + * For hint 0x700 (special LL/SC loop barrier), treat as full barrier.\n>> + *\n>> + * See LoongArch Reference Manual v1.10, Section 4.2.2 for details.\n>> + */\n>>   static bool trans_dbar(DisasContext *ctx, arg_dbar * a)\n>>   {\n>> -    tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);\n>> +    int hint = a->imm;\n>> +    TCGBar bar_flags = 0;\n>> +\n>> +    /* Reserved/no-op hints: 0xf and 0x1f */\n>> +    if (hint == 0xf || hint == 0x1f) {\n>> +        return true;\n>> +    }\n>> +\n>> +    /* If the CPU does not support fine-grained hints,or for the \n>> special LL/SC\n>> +     * loop barrier (0x700), emit a full barrier.\n>> +     */\n>> +    if (!avail_DBAR_HINT(ctx) || hint == 0x700) {\n>> +        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n>> +        return true;\n>> +    }\n>> +\n>> +    /*\n>> +     * Fine-grained hint decoding:\n>> +     * Bits 3-0 control which accesses must be ordered.\n>> +     * Bit3: barrier for previous read (0: true, 1: false)\n>> +     * Bit2: barrier for previous write (0: true, 1: false)\n>> +     * Bit1: barrier for succeeding read (0: true, 1: false)\n>> +     * Bit0: barrier for succeeding write (0: true, 1: false)\n> Hi Song,\n>\n> This is much better than before, I think it will be better if some \n> comments for BIT4 is added here showing it is discarded here.\n>> +     *\n>> +     * For each combination, we set the corresponding TCG_MO_* flag \n>> if both\n>> +     * sides of the barrier require ordering.\n>> +     */\n>> +\n>> +    bool prev_rd = !(hint & 0x08); /* bit3 */\n>> +    bool prev_wr = !(hint & 0x04); /* bit2 */\n>> +    bool succ_rd = !(hint & 0x02); /* bit1 */\n>> +    bool succ_wr = !(hint & 0x01); /* bit0 */\n>> +\n>> +    if (prev_rd) {\n>> +        bar_flags |= TCG_MO_LD_LD | TCG_MO_LD_ST;\n>> +    }\n>> +    if (prev_wr) {\n>> +        bar_flags |= TCG_MO_ST_LD | TCG_MO_ST_ST;\n>> +    }\n>> +    if (succ_rd) {\n>> +        bar_flags |= TCG_MO_LD_LD | TCG_MO_ST_LD;\n>> +    }\n>> +    if (succ_wr) {\n>> +        bar_flags |= TCG_MO_ST_ST | TCG_MO_LD_ST;\n>> +    }\n> Previously I hear that TCG_MO_LD_ST should be default enabled on \n> LoongArch, but I am not sure. Is that correct?\n>\nHi,\n\nI don't quite understand the issue you're referring to. Could you please \nexplain it in more detail?\n\nThanks.\nSong Gao\n\n\n> The others looks good to me.\n>\n> Regards\n> Bibo Mao\n>\n>> +\n>> +    if (bar_flags == 0) {\n>> +        bar_flags = TCG_MO_ALL;\n>> +    }\n>> +\n>> +    tcg_gen_mb(bar_flags | TCG_BAR_SC);\n>>       return true;\n>> -}\n>> + }\n>>     static bool trans_ibar(DisasContext *ctx, arg_ibar *a)\n>>   {\n>> diff --git a/target/loongarch/tcg/translate.c \n>> b/target/loongarch/tcg/translate.c\n>> index b9ed13d19c..49280b1dd3 100644\n>> --- a/target/loongarch/tcg/translate.c\n>> +++ b/target/loongarch/tcg/translate.c\n>> @@ -149,6 +149,7 @@ static void \n>> loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n>>         ctx->cpucfg1 = env->cpucfg[1];\n>>       ctx->cpucfg2 = env->cpucfg[2];\n>> +    ctx->cpucfg3 = env->cpucfg[3];\n>>   }\n>>     static void loongarch_tr_tb_start(DisasContextBase *dcbase, \n>> CPUState *cs)\n>> diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\n>> index ba1c89e57b..8aa8325dc6 100644\n>> --- a/target/loongarch/translate.h\n>> +++ b/target/loongarch/translate.h\n>> @@ -43,6 +43,8 @@\n>>   #define avail_LLACQ_SCREL(C)    (FIELD_EX32((C)->cpucfg2, CPUCFG2, \n>> LLACQ_SCREL))\n>>   #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))\n>>   +#define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, \n>> DBAR_HINTS))\n>> +\n>>   /*\n>>    * If an operation is being performed on less than TARGET_LONG_BITS,\n>>    * it may require the inputs to be sign- or zero-extended; which will\n>> @@ -66,6 +68,7 @@ typedef struct DisasContext {\n>>       bool va32; /* 32-bit virtual address */\n>>       uint32_t cpucfg1;\n>>       uint32_t cpucfg2;\n>> +    uint32_t cpucfg3;\n>>   } DisasContext;\n>>     void generate_exception(DisasContext *ctx, int excp);\n>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvpfd0nRTz1y2d\n\tfor ; Tue, 14 Apr 2026 12:50:15 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCTqV-0003Lw-DY; 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Linux loongarch64; rv:68.0) Gecko/20100101\n Thunderbird/68.7.0","MIME-Version":"1.0","In-Reply-To":"<331159fe-8596-e406-32d5-c9c8c2ad6f8b@loongson.cn>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"8bit","Content-Language":"en-US","X-CM-TRANSID":"qMiowJCxOME5q91p25ZsAA--.62094S3","X-CM-SenderInfo":"5jdr20tqj6z05rqj20fqof0/","X-Coremail-Antispam":"1Uk129KBj93XoW3JryDWFy7ZF15tr4fZr48Xwc_yoW3JFW8pr\n 1kCFWUKFWUtr93Aw18JrW5ZFy5ZrWxG3W2q34IqFyrur47Gr10gr10grZ0gF17Gr4kXF18\n ZF18ZwsrZF9xXFXCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa\n sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU\n 0xBIdaVrnRJUUUvYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2\n IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v\n e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI\n 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2\n 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc\n 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAF\n wI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcVAKI48JMxk0xIA0c2IEe2xFo4\n CEbIxvr21l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG\n 67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMI\n IYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E\n 14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJV\n W8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UWHqcU\n UUUU=","Received-SPF":"pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn","X-Spam_score_int":"-49","X-Spam_score":"-5.0","X-Spam_bar":"-----","X-Spam_report":"(-5.0 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-3.135,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3677067,"web_url":"http://patchwork.ozlabs.org/comment/3677067/","msgid":"","list_archive_url":null,"date":"2026-04-14T08:34:54","subject":"Re: [PATCH v2] target/loongarch: Add support for dbar hint variants","submitter":{"id":78914,"url":"http://patchwork.ozlabs.org/api/people/78914/","name":"Bibo Mao","email":"maobibo@loongson.cn"},"content":"On 2026/4/14 上午10:50, gaosong wrote:\n> 在 2026/4/13 下午5:32, Bibo Mao 写道:\n>>\n>>\n>> On 2026/4/10 上午11:37, Song Gao wrote:\n>>> LoongArch architecture (since LA664) introduces fine-grained dbar\n>>> hints that allow controlling which memory accesses are ordered by\n>>> the barrier. Previously, all dbar instructions were treated as a\n>>> full barrier (TCG_MO_ALL | TCG_BAR_SC).\n>>>\n>>> This patch adds support for decoding dbar hints and emitting the\n>>> appropriate TCG memory barrier flags. For CPUs that do not advertise\n>>> the DBAR_HINTS feature (cpucfg3.DBAR_HINTS = 0), all dbar hints\n>>> fall back to a full barrier, preserving compatibility.\n>>>\n>>> The hint encoding follows the LoongArch v1.10 specification:\n>>>   * Bit3: barrier for previous read (0: true, 1: false)\n>>>   * Bit2: barrier for previous write (0: true, 1: false)\n>>>   * Bit1: barrier for succeeding read (0: true, 1: false)\n>>>   * Bit0: barrier for succeeding write (0: true, 1: false)\n>>>\n>>> The mapping to TCG memory order flags is as follows:\n>>>    TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_LD_ST;\n>>>    TCG_BAR_SC |TCG_MO_ST_LD | TCG_MO_ST_ST;\n>>>    TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_ST_LD;\n>>>    TCG_BAR_SC |TCG_MO_ST_ST | TCG_MO_LD_ST;\n>>>\n>>> Special hint handling:\n>>> - hint 0x700: LL/SC loop barrier, treated as a full barrier as \n>>> recommended.\n>>> - hint 0xf and 0x1f: reserved/no-op, treated as no operation\n>>>\n>>> Signed-off-by: Song Gao \n>>> ---\n>>>   target/loongarch/cpu.c                        |  4 ++\n>>>   .../tcg/insn_trans/trans_memory.c.inc         | 62 ++++++++++++++++++-\n>>>   target/loongarch/tcg/translate.c              |  1 +\n>>>   target/loongarch/translate.h                  |  3 +\n>>>   4 files changed, 68 insertions(+), 2 deletions(-)\n>>>\n>>> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\n>>> index e22568c84a..d8d106b07e 100644\n>>> --- a/target/loongarch/cpu.c\n>>> +++ b/target/loongarch/cpu.c\n>>> @@ -455,6 +455,10 @@ static void loongarch_max_initfn(Object *obj)\n>>>           data = FIELD_DP32(data, CPUCFG2, LLACQ_SCREL, 1);\n>>>           data = FIELD_DP32(data, CPUCFG2, SCQ, 1);\n>>>           cpu->env.cpucfg[2] = data;\n>>> +\n>>> +        data = cpu->env.cpucfg[3];\n>>> +        data = FIELD_DP32(data, CPUCFG3, DBAR_HINTS, 1);\n>>> +        cpu->env.cpucfg[3] = data;\n>>>       }\n>>>   }\n>>>   diff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc \n>>> b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n>>> index e287d46363..e1146fe9ec 100644\n>>> --- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n>>> +++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n>>> @@ -137,11 +137,69 @@ static bool trans_preldx(DisasContext *ctx, \n>>> arg_preldx * a)\n>>>       return true;\n>>>   }\n>>>   +/*\n>>> + * Decode dbar hint and emit appropriate TCG memory barrier.\n>>> + *\n>>> + * The hint is a 5-bit field (0-31) encoded in the instruction.\n>>> + * For hint 0x700 (special LL/SC loop barrier), treat as full barrier.\n>>> + *\n>>> + * See LoongArch Reference Manual v1.10, Section 4.2.2 for details.\n>>> + */\n>>>   static bool trans_dbar(DisasContext *ctx, arg_dbar * a)\n>>>   {\n>>> -    tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);\n>>> +    int hint = a->imm;\n>>> +    TCGBar bar_flags = 0;\n>>> +\n>>> +    /* Reserved/no-op hints: 0xf and 0x1f */\n>>> +    if (hint == 0xf || hint == 0x1f) {\n>>> +        return true;\n>>> +    }\n>>> +\n>>> +    /* If the CPU does not support fine-grained hints,or for the \n>>> special LL/SC\n>>> +     * loop barrier (0x700), emit a full barrier.\n>>> +     */\n>>> +    if (!avail_DBAR_HINT(ctx) || hint == 0x700) {\n>>> +        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);\n>>> +        return true;\n>>> +    }\n>>> +\n>>> +    /*\n>>> +     * Fine-grained hint decoding:\n>>> +     * Bits 3-0 control which accesses must be ordered.\n>>> +     * Bit3: barrier for previous read (0: true, 1: false)\n>>> +     * Bit2: barrier for previous write (0: true, 1: false)\n>>> +     * Bit1: barrier for succeeding read (0: true, 1: false)\n>>> +     * Bit0: barrier for succeeding write (0: true, 1: false)\n>> Hi Song,\n>>\n>> This is much better than before, I think it will be better if some \n>> comments for BIT4 is added here showing it is discarded here.\n>>> +     *\n>>> +     * For each combination, we set the corresponding TCG_MO_* flag \n>>> if both\n>>> +     * sides of the barrier require ordering.\n>>> +     */\n>>> +\n>>> +    bool prev_rd = !(hint & 0x08); /* bit3 */\n>>> +    bool prev_wr = !(hint & 0x04); /* bit2 */\n>>> +    bool succ_rd = !(hint & 0x02); /* bit1 */\n>>> +    bool succ_wr = !(hint & 0x01); /* bit0 */\n>>> +\n>>> +    if (prev_rd) {\n>>> +        bar_flags |= TCG_MO_LD_LD | TCG_MO_LD_ST;\n>>> +    }\n>>> +    if (prev_wr) {\n>>> +        bar_flags |= TCG_MO_ST_LD | TCG_MO_ST_ST;\n>>> +    }\n>>> +    if (succ_rd) {\n>>> +        bar_flags |= TCG_MO_LD_LD | TCG_MO_ST_LD;\n>>> +    }\n>>> +    if (succ_wr) {\n>>> +        bar_flags |= TCG_MO_ST_ST | TCG_MO_LD_ST;\n>>> +    }\n>> Previously I hear that TCG_MO_LD_ST should be default enabled on \n>> LoongArch, but I am not sure. Is that correct?\n>>\n> Hi,\n> \n> I don't quite understand the issue you're referring to. Could you please \n> explain it in more detail?\nThat is not relative with this patch, just skip it.\n\nRegards\nBibo Mao\n> \n> Thanks.\n> Song Gao\n> \n> \n>> The others looks good to me.\n>>\n>> Regards\n>> Bibo Mao\n>>\n>>> +\n>>> +    if (bar_flags == 0) {\n>>> +        bar_flags = TCG_MO_ALL;\n>>> +    }\n>>> +\n>>> +    tcg_gen_mb(bar_flags | TCG_BAR_SC);\n>>>       return true;\n>>> -}\n>>> + }\n>>>     static bool trans_ibar(DisasContext *ctx, arg_ibar *a)\n>>>   {\n>>> diff --git a/target/loongarch/tcg/translate.c \n>>> b/target/loongarch/tcg/translate.c\n>>> index b9ed13d19c..49280b1dd3 100644\n>>> --- a/target/loongarch/tcg/translate.c\n>>> +++ b/target/loongarch/tcg/translate.c\n>>> @@ -149,6 +149,7 @@ static void \n>>> loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n>>>         ctx->cpucfg1 = env->cpucfg[1];\n>>>       ctx->cpucfg2 = env->cpucfg[2];\n>>> +    ctx->cpucfg3 = env->cpucfg[3];\n>>>   }\n>>>     static void loongarch_tr_tb_start(DisasContextBase *dcbase, \n>>> CPUState *cs)\n>>> diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\n>>> index ba1c89e57b..8aa8325dc6 100644\n>>> --- a/target/loongarch/translate.h\n>>> +++ b/target/loongarch/translate.h\n>>> @@ -43,6 +43,8 @@\n>>>   #define avail_LLACQ_SCREL(C)    (FIELD_EX32((C)->cpucfg2, CPUCFG2, \n>>> LLACQ_SCREL))\n>>>   #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))\n>>>   +#define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, \n>>> DBAR_HINTS))\n>>> +\n>>>   /*\n>>>    * If an operation is being performed on less than TARGET_LONG_BITS,\n>>>    * it may require the inputs to be sign- or zero-extended; which will\n>>> @@ -66,6 +68,7 @@ typedef struct DisasContext {\n>>>       bool va32; /* 32-bit virtual address */\n>>>       uint32_t cpucfg1;\n>>>       uint32_t cpucfg2;\n>>> +    uint32_t cpucfg3;\n>>>   } DisasContext;\n>>>     void generate_exception(DisasContext *ctx, int excp);\n>>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)","Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvyNm60tJz1y2d\n\tfor ; Tue, 14 Apr 2026 18:38:47 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCZHU-000455-FT; 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