[{"id":3675536,"web_url":"http://patchwork.ozlabs.org/comment/3675536/","msgid":"<9AD3250E-71F9-4B8B-95B3-01C56AF885F9@unpredictable.fr>","list_archive_url":null,"date":"2026-04-09T22:21:16","subject":"Re: [PATCH v6 5/6] target/arm/emulate: add atomic, compare-and-swap,\n and PAC load","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"content":"> On 10. Apr 2026, at 00:06, Lucas Amaral wrote:\n> \n> Add emulation for remaining ISV=0 load/store instruction classes.\n> \nWith the caveat of “why does this even happen”:\n\nMaybe there should be a restriction to put a warning message\nsomewhere if an op happens on a non-MMIO range…\n\nReviewed-by: Mohamed Mediouni \n\n\n> Atomic memory operations (DDI 0487 C3.3.2):\n> - LDADD, LDCLR, LDEOR, LDSET: arithmetic/logic atomics\n> - LDSMAX, LDSMIN, LDUMAX, LDUMIN: signed/unsigned min/max\n> - SWP: atomic swap\n> Non-atomic read-modify-write, sufficient for MMIO where concurrent\n> access is not a concern. Acquire/release semantics are ignored.\n> \n> Compare-and-swap (DDI 0487 C3.3.1):\n> - CAS/CASA/CASAL/CASL: single-register compare-and-swap\n> - CASP/CASPA/CASPAL/CASPL: register-pair compare-and-swap\n> CASP validates even register pairs; odd or r31 returns UNHANDLED.\n> \n> Load with PAC (DDI 0487 C6.2.121):\n> - LDRAA/LDRAB: pointer-authenticated load, offset/pre-indexed\n> Pointer authentication is not emulated (equivalent to auth always\n> succeeding), which is correct for MMIO since PAC is a software\n> security mechanism, not a memory access semantic.\n> \n> Decodetree differences from TCG:\n> - %ldra_imm extracts the raw S:imm9 field; the handler scales by\n> << 3. TCG applies !function=times_8 in the formatter.\n> - @ldra uses wildcards for fixed opcode bits that TCG locks down\n> (bits 31:30, bit 20, bit 11); the fixed bits are matched by the\n> instruction pattern instead.\n> - @cas is an explicit format template; TCG uses inline field\n> extraction.\n> \n> CASP uses two explicit decode patterns for the 32/64-bit size\n> variants. LDRA's offset immediate is stored raw in the decode;\n> the handler scales by << 3.\n> \n> Signed-off-by: Lucas Amaral \n> ---\n> target/arm/emulate/a64-ldst.decode | 45 ++++++\n> target/arm/emulate/arm_emulate.c | 233 +++++++++++++++++++++++++++++\n> 2 files changed, 278 insertions(+)\n> \n> diff --git a/target/arm/emulate/a64-ldst.decode b/target/arm/emulate/a64-ldst.decode\n> index fadf6fd2..9292bfdf 100644\n> --- a/target/arm/emulate/a64-ldst.decode\n> +++ b/target/arm/emulate/a64-ldst.decode\n> @@ -16,6 +16,16 @@\n> # Load/store pair (GPR and SIMD/FP)\n> &ldstpair rt2 rt rn imm sz sign w p\n> \n> +# Atomic memory operations\n> +&atomic rs rn rt a r sz\n> +\n> +# Compare-and-swap\n> +&cas rs rn rt sz a r\n> +\n> +# Load with PAC (LDRAA/LDRAB, FEAT_PAuth)\n> +%ldra_imm 22:s1 12:9\n> +&ldra rt rn imm m w\n> +\n> # Load/store register offset\n> &ldst rm rn rt sign ext sz opt s\n> \n> @@ -36,6 +46,15 @@\n> # Load/store pair: imm7 is signed, scaled by element size in handler\n> @ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair\n> \n> +# Atomics\n> +@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic\n> +\n> +# Compare-and-swap: sz extracted by pattern (CAS) or set constant (CASP)\n> +@cas .. ...... . a:1 . rs:5 r:1 ..... rn:5 rt:5 &cas\n> +\n> +# Load with PAC\n> +@ldra .. ... . .. m:1 . . ......... w:1 . rn:5 rt:5 &ldra imm=%ldra_imm\n> +\n> # Load/store register offset\n> @ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst\n> \n> @@ -241,6 +260,32 @@ STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=\n> LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0\n> LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4\n> \n> +### Compare-and-swap\n> +\n> +# CAS / CASA / CASAL / CASL\n> +CAS sz:2 001000 1 . 1 ..... . 11111 ..... ..... @cas\n> +\n> +# CASP / CASPA / CASPAL / CASPL (pair: Rt,Rt+1 and Rs,Rs+1)\n> +CASP 00 001000 0 . 1 ..... . 11111 ..... ..... @cas sz=2\n> +CASP 01 001000 0 . 1 ..... . 11111 ..... ..... @cas sz=3\n> +\n> +### Atomic memory operations\n> +\n> +LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic\n> +LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic\n> +LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic\n> +LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic\n> +LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic\n> +LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic\n> +LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic\n> +LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic\n> +SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic\n> +\n> +### Load with PAC (FEAT_PAuth)\n> +\n> +# LDRAA (M=0) / LDRAB (M=1), offset (W=0) / pre-indexed (W=1)\n> +LDRA 11 111 0 00 . . 1 ......... . 1 ..... ..... @ldra\n> +\n> ### System instructions — DC cache maintenance\n> \n> # SYS with CRn=C7 covers all data cache operations (DC CIVAC, CVAC, etc.).\n> diff --git a/target/arm/emulate/arm_emulate.c b/target/arm/emulate/arm_emulate.c\n> index 7f876355..6601c9dc 100644\n> --- a/target/arm/emulate/arm_emulate.c\n> +++ b/target/arm/emulate/arm_emulate.c\n> @@ -547,6 +547,239 @@ static bool trans_LDXP(DisasContext *ctx, arg_stxr *a)\n> return true;\n> }\n> \n> +/*\n> + * Atomic memory operations (DDI 0487 C3.3.2)\n> + *\n> + * Non-atomic read-modify-write; sufficient for MMIO.\n> + * Acquire/release semantics ignored (sequentially consistent by design).\n> + */\n> +\n> +typedef uint64_t (*atomic_op_fn)(uint64_t old, uint64_t operand, int bits);\n> +\n> +static uint64_t atomic_add(uint64_t old, uint64_t op, int bits)\n> +{\n> + return old + op;\n> +}\n> +\n> +static uint64_t atomic_clr(uint64_t old, uint64_t op, int bits)\n> +{\n> + return old & ~op;\n> +}\n> +\n> +static uint64_t atomic_eor(uint64_t old, uint64_t op, int bits)\n> +{\n> + return old ^ op;\n> +}\n> +\n> +static uint64_t atomic_set(uint64_t old, uint64_t op, int bits)\n> +{\n> + return old | op;\n> +}\n> +\n> +static uint64_t atomic_smax(uint64_t old, uint64_t op, int bits)\n> +{\n> + int64_t a = sextract64(old, 0, bits);\n> + int64_t b = sextract64(op, 0, bits);\n> + return (a >= b) ? old : op;\n> +}\n> +\n> +static uint64_t atomic_smin(uint64_t old, uint64_t op, int bits)\n> +{\n> + int64_t a = sextract64(old, 0, bits);\n> + int64_t b = sextract64(op, 0, bits);\n> + return (a <= b) ? old : op;\n> +}\n> +\n> +static uint64_t atomic_umax(uint64_t old, uint64_t op, int bits)\n> +{\n> + uint64_t mask = (bits == 64) ? UINT64_MAX : (1ULL << bits) - 1;\n> + return ((old & mask) >= (op & mask)) ? old : op;\n> +}\n> +\n> +static uint64_t atomic_umin(uint64_t old, uint64_t op, int bits)\n> +{\n> + uint64_t mask = (bits == 64) ? UINT64_MAX : (1ULL << bits) - 1;\n> + return ((old & mask) <= (op & mask)) ? old : op;\n> +}\n> +\n> +static bool do_atomic(DisasContext *ctx, arg_atomic *a, atomic_op_fn fn)\n> +{\n> + int esize = 1 << a->sz;\n> + int bits = 8 * esize;\n> + uint64_t va = base_read(ctx, a->rn);\n> + uint8_t buf[8];\n> +\n> + if (mem_read(ctx, va, buf, esize) != 0) {\n> + return true;\n> + }\n> +\n> + uint64_t old = mem_ld(ctx, buf, esize);\n> + uint64_t operand = gpr_read(ctx, a->rs);\n> + uint64_t result = fn(old, operand, bits);\n> +\n> + mem_st(ctx, buf, esize, result);\n> + if (mem_write(ctx, va, buf, esize) != 0) {\n> + return true;\n> + }\n> +\n> + /* Rt receives the old value (before modification) */\n> + gpr_write(ctx, a->rt, old);\n> + return true;\n> +}\n> +\n> +static bool trans_LDADD(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_add);\n> +}\n> +\n> +static bool trans_LDCLR(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_clr);\n> +}\n> +\n> +static bool trans_LDEOR(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_eor);\n> +}\n> +\n> +static bool trans_LDSET(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_set);\n> +}\n> +\n> +static bool trans_LDSMAX(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_smax);\n> +}\n> +\n> +static bool trans_LDSMIN(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_smin);\n> +}\n> +\n> +static bool trans_LDUMAX(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_umax);\n> +}\n> +\n> +static bool trans_LDUMIN(DisasContext *ctx, arg_atomic *a)\n> +{\n> + return do_atomic(ctx, a, atomic_umin);\n> +}\n> +\n> +static bool trans_SWP(DisasContext *ctx, arg_atomic *a)\n> +{\n> + int esize = 1 << a->sz;\n> + uint64_t va = base_read(ctx, a->rn);\n> + uint8_t buf[8];\n> +\n> + if (mem_read(ctx, va, buf, esize) != 0) {\n> + return true;\n> + }\n> +\n> + uint64_t old = mem_ld(ctx, buf, esize);\n> + mem_st(ctx, buf, esize, gpr_read(ctx, a->rs));\n> + if (mem_write(ctx, va, buf, esize) != 0) {\n> + return true;\n> + }\n> +\n> + gpr_write(ctx, a->rt, old);\n> + return true;\n> +}\n> +\n> +/* Compare-and-swap: CAS, CASP (DDI 0487 C3.3.1) */\n> +\n> +static bool trans_CAS(DisasContext *ctx, arg_cas *a)\n> +{\n> + int esize = 1 << a->sz;\n> + uint64_t va = base_read(ctx, a->rn);\n> + uint8_t buf[8];\n> +\n> + if (mem_read(ctx, va, buf, esize) != 0) {\n> + return true;\n> + }\n> +\n> + uint64_t current = mem_ld(ctx, buf, esize);\n> + uint64_t mask = (esize == 8) ? UINT64_MAX : (1ULL << (8 * esize)) - 1;\n> + uint64_t compare = gpr_read(ctx, a->rs) & mask;\n> +\n> + if ((current & mask) == compare) {\n> + uint64_t newval = gpr_read(ctx, a->rt) & mask;\n> + mem_st(ctx, buf, esize, newval);\n> + if (mem_write(ctx, va, buf, esize) != 0) {\n> + return true;\n> + }\n> + }\n> +\n> + /* Rs receives the old memory value (whether or not swap occurred) */\n> + gpr_write(ctx, a->rs, current);\n> + return true;\n> +}\n> +\n> +/* CASP: compare-and-swap pair (Rs,Rs+1 compared; Rt,Rt+1 stored) */\n> +static bool trans_CASP(DisasContext *ctx, arg_cas *a)\n> +{\n> + /* CASP requires even register pairs; odd or r31 is UNPREDICTABLE */\n> + if ((a->rs & 1) || a->rs >= 31 || (a->rt & 1) || a->rt >= 31) {\n> + return false;\n> + }\n> +\n> + int esize = 1 << a->sz; /* per-register size */\n> + uint64_t va = base_read(ctx, a->rn);\n> + uint8_t buf[16];\n> +\n> + if (mem_read(ctx, va, buf, 2 * esize) != 0) {\n> + return true;\n> + }\n> + uint64_t cur1 = mem_ld(ctx, buf, esize);\n> + uint64_t cur2 = mem_ld(ctx, buf + esize, esize);\n> +\n> + uint64_t mask = (esize == 8) ? UINT64_MAX : (1ULL << (8 * esize)) - 1;\n> + uint64_t cmp1 = gpr_read(ctx, a->rs) & mask;\n> + uint64_t cmp2 = gpr_read(ctx, a->rs + 1) & mask;\n> +\n> + if ((cur1 & mask) == cmp1 && (cur2 & mask) == cmp2) {\n> + uint64_t new1 = gpr_read(ctx, a->rt) & mask;\n> + uint64_t new2 = gpr_read(ctx, a->rt + 1) & mask;\n> + mem_st(ctx, buf, esize, new1);\n> + mem_st(ctx, buf + esize, esize, new2);\n> + if (mem_write(ctx, va, buf, 2 * esize) != 0) {\n> + return true;\n> + }\n> + }\n> +\n> + gpr_write(ctx, a->rs, cur1);\n> + gpr_write(ctx, a->rs + 1, cur2);\n> + return true;\n> +}\n> +\n> +/*\n> + * Load with PAC: LDRAA / LDRAB (FEAT_PAuth)\n> + * (DDI 0487 C6.2.121)\n> + *\n> + * Pointer authentication is not emulated -- the base register is used\n> + * directly (equivalent to auth always succeeding).\n> + */\n> +\n> +static bool trans_LDRA(DisasContext *ctx, arg_ldra *a)\n> +{\n> + int64_t offset = (int64_t)a->imm << 3; /* S:imm9, scaled by 8 */\n> + uint64_t base = base_read(ctx, a->rn);\n> + uint64_t va = base + offset; /* auth not emulated */\n> + uint8_t buf[8];\n> +\n> + if (mem_read(ctx, va, buf, 8) != 0) {\n> + return true;\n> + }\n> +\n> + gpr_write(ctx, a->rt, mem_ld(ctx, buf, 8));\n> +\n> + if (a->w) {\n> + base_write(ctx, a->rn, va);\n> + }\n> + return true;\n> +}\n> +\n> /* PRFM, DC cache maintenance -- treated as NOP */\n> static bool trans_NOP(DisasContext *ctx, arg_NOP *a)\n> {\n> -- \n> 2.52.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=Rlg6cmBH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsDv61MJwz1yCv\n\tfor ; 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