[{"id":3675581,"web_url":"http://patchwork.ozlabs.org/comment/3675581/","msgid":"","list_archive_url":null,"date":"2026-04-10T01:05:15","subject":"Re: [PATCH 1/2] target/riscv: preserve RV32 henvcfgh on henvcfg\n writes","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Fri, Apr 10, 2026 at 3:27 AM Bruno Sa wrote:\n>\n> On RV32, STCE/ADUE/PBMTE/DTE are implemented in henvcfgh. A write to\n> henvcfg should therefore only update the low 32 bits of env->henvcfg.\n>\n> The current write_henvcfg() path overwrites env->henvcfg with the\n> low-half value and clears any bits previously written via henvcfgh.\n>\n> Preserve the upper 32 bits on RV32 henvcfg writes and keep the existing\n> RV64 behaviour unchanged.\n>\n> Signed-off-by: Bruno Sa \n\nReviewed-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/csr.c | 10 +++++++++-\n> 1 file changed, 9 insertions(+), 1 deletion(-)\n>\n> diff --git a/target/riscv/csr.c b/target/riscv/csr.c\n> index 7948188356..d322bdbd47 100644\n> --- a/target/riscv/csr.c\n> +++ b/target/riscv/csr.c\n> @@ -3326,7 +3326,15 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,\n> }\n> }\n>\n> - env->henvcfg = val & mask;\n> + if (riscv_cpu_mxl(env) == MXL_RV32) {\n> + /*\n> + * RV32 stores STCE/ADUE/PBMTE/DTE in henvcfgh, so a low-half henvcfg\n> + * write must not clobber the upper 32 bits.\n> + */\n> + env->henvcfg = (env->henvcfg & ~0xFFFFFFFFULL) | (val & mask);\n> + } else {\n> + env->henvcfg = val & mask;\n> + }\n> if ((env->henvcfg & HENVCFG_DTE) == 0) {\n> env->vsstatus &= ~MSTATUS_SDT;\n> }\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=EjD0mIIV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 09 Apr 2026\n 18:05:41 -0700 (PDT)","MIME-Version":"1.0","References":"<20260409155344.2849233-1-bruno.vilaca.sa@gmail.com>\n <20260409155344.2849233-2-bruno.vilaca.sa@gmail.com>","In-Reply-To":"<20260409155344.2849233-2-bruno.vilaca.sa@gmail.com>","From":"Alistair Francis ","Date":"Fri, 10 Apr 2026 11:05:15 +1000","X-Gm-Features":"AQROBzACqyk9RA5mGvD0Uj14P5AEkITpxANbBhqpkvytfsFBHAP0YXuQiDsGIps","Message-ID":"\n ","Subject":"Re: [PATCH 1/2] target/riscv: preserve RV32 henvcfgh on henvcfg\n writes","To":"Bruno Sa ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,\n alistair.francis@wdc.com, liwei1518@gmail.com, dbarboza@ventanamicro.com,\n zhiwei_liu@linux.alibaba.com","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::632;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x632.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]