[{"id":3675445,"web_url":"http://patchwork.ozlabs.org/comment/3675445/","msgid":"<20260409163341.GP41863@bill-the-cat>","list_archive_url":null,"date":"2026-04-09T16:33:41","subject":"Re: [PATCH 3/9] arm: dts: Add HPE GSC device tree","submitter":{"id":65875,"url":"http://patchwork.ozlabs.org/api/people/65875/","name":"Tom Rini","email":"trini@konsulko.com"},"content":"On Wed, Apr 08, 2026 at 07:24:15PM +0000, Jorge Cisneros wrote:\n\n> Add device tree for the HPE GSC SoC including:\n> - Dual Cortex-A35 cores with spin-table enable method\n> - GICv3 interrupt controller\n> - NS16550A compatible UART\n> - GXP timer and SPI/I2C controllers (shared IP blocks)\n> - Two Cadence GEM Ethernet MACs with SGMII PHYs\n> - Synopsys DWC MSHC eMMC controller\n> - GSC watchdog timer\n> - Memory-mapped virtual EEPROM for VPD storage\n> - Fixed clock definitions for peripheral buses\n> \n> Signed-off-by: Jorge Cisneros \n> ---\n> arch/arm/dts/hpe-gsc.dts | 146 +++++++++++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 146 insertions(+)\n\nWhat is the status of getting this supported in the upstream kernel?\nI do see dts/upstream/src/arm/hpe/hpe-gxp.dtsi for example. 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