[{"id":3675209,"web_url":"http://patchwork.ozlabs.org/comment/3675209/","msgid":"<7fcff35b-383d-4dac-bfcc-3d889db35df0@linaro.org>","list_archive_url":null,"date":"2026-04-09T09:41:38","subject":"Re: [PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 9/4/26 08:40, Vivian Wang wrote:\n> These unit addresses should have been in hex, not decimal, as per de\n> facto convention [1]. Fix them.\n> \n> Link: https://lore.kernel.org/devicetree-spec/CAL_JsqJFv3+UJ-bjLGk0i7Wc+spsowCrqQZ_s3P4gN8r1W-Q-w@mail.gmail.com/ # [1]\n> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>\n> ---\n>   hw/riscv/sifive_u.c | 9 +++++----\n>   hw/riscv/spike.c    | 4 ++--\n>   hw/riscv/virt.c     | 4 ++--\n>   3 files changed, 9 insertions(+), 8 deletions(-)\n> \n> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c\n> index 7ec67b2565..54f3bcc3b2 100644\n> --- a/hw/riscv/sifive_u.c\n> +++ b/hw/riscv/sifive_u.c\n> @@ -168,8 +168,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n>   \n>       for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {\n>           int cpu_phandle = phandle++;\n> -        nodename = g_strdup_printf(\"/cpus/cpu@%d\", cpu);\n> -        char *intc = g_strdup_printf(\"/cpus/cpu@%d/interrupt-controller\", cpu);\n> +        nodename = g_strdup_printf(\"/cpus/cpu@%x\", (unsigned)cpu);\n> +        char *intc = g_strdup_printf(\"/cpus/cpu@%x/interrupt-controller\",\n> +                                     (unsigned)cpu);\n\nNo need to cast to unsigned explicitly, otherwise:\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bR+sM89s;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::432;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675550,"web_url":"http://patchwork.ozlabs.org/comment/3675550/","msgid":"<CAKmqyKPO8HjaoLdC61rTiNkawFfwb6e9YtAq0c2YBcA-fTtXjQ@mail.gmail.com>","list_archive_url":null,"date":"2026-04-09T23:10:40","subject":"Re: [PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 9, 2026 at 4:42 PM Vivian Wang <wangruikang@iscas.ac.cn> wrote:\n>\n> These unit addresses should have been in hex, not decimal, as per de\n> facto convention [1]. Fix them.\n>\n> Link: https://lore.kernel.org/devicetree-spec/CAL_JsqJFv3+UJ-bjLGk0i7Wc+spsowCrqQZ_s3P4gN8r1W-Q-w@mail.gmail.com/ # [1]\n> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>\n\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\n\nAlistair\n\n> ---\n>  hw/riscv/sifive_u.c | 9 +++++----\n>  hw/riscv/spike.c    | 4 ++--\n>  hw/riscv/virt.c     | 4 ++--\n>  3 files changed, 9 insertions(+), 8 deletions(-)\n>\n> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c\n> index 7ec67b2565..54f3bcc3b2 100644\n> --- a/hw/riscv/sifive_u.c\n> +++ b/hw/riscv/sifive_u.c\n> @@ -168,8 +168,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n>\n>      for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {\n>          int cpu_phandle = phandle++;\n> -        nodename = g_strdup_printf(\"/cpus/cpu@%d\", cpu);\n> -        char *intc = g_strdup_printf(\"/cpus/cpu@%d/interrupt-controller\", cpu);\n> +        nodename = g_strdup_printf(\"/cpus/cpu@%x\", (unsigned)cpu);\n> +        char *intc = g_strdup_printf(\"/cpus/cpu@%x/interrupt-controller\",\n> +                                     (unsigned)cpu);\n>          qemu_fdt_add_subnode(fdt, nodename);\n>          /* cpu 0 is the management hart that does not have mmu */\n>          if (cpu != 0) {\n> @@ -198,7 +199,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n>      cells =  g_new0(uint32_t, ms->smp.cpus * 4);\n>      for (cpu = 0; cpu < ms->smp.cpus; cpu++) {\n>          nodename =\n> -            g_strdup_printf(\"/cpus/cpu@%d/interrupt-controller\", cpu);\n> +            g_strdup_printf(\"/cpus/cpu@%x/interrupt-controller\", (unsigned)cpu);\n>          uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);\n>          cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);\n>          cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);\n> @@ -249,7 +250,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n>      cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);\n>      for (cpu = 0; cpu < ms->smp.cpus; cpu++) {\n>          nodename =\n> -            g_strdup_printf(\"/cpus/cpu@%d/interrupt-controller\", cpu);\n> +            g_strdup_printf(\"/cpus/cpu@%x/interrupt-controller\", (unsigned)cpu);\n>          uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);\n>          /* cpu 0 is the management hart that does not have S-mode */\n>          if (cpu == 0) {\n> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c\n> index 35c696f891..cac01ea1ff 100644\n> --- a/hw/riscv/spike.c\n> +++ b/hw/riscv/spike.c\n> @@ -105,8 +105,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,\n>          for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {\n>              cpu_phandle = phandle++;\n>\n> -            cpu_name = g_strdup_printf(\"/cpus/cpu@%d\",\n> -                s->soc[socket].hartid_base + cpu);\n> +            cpu_name = g_strdup_printf(\"/cpus/cpu@%\" PRIx32,\n> +                s->soc[socket].hartid_base + (uint32_t)cpu);\n>              qemu_fdt_add_subnode(fdt, cpu_name);\n>              if (is_32_bit) {\n>                  qemu_fdt_setprop_string(fdt, cpu_name, \"mmu-type\", \"riscv,sv32\");\n> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\n> index a1c323e66d..42a83dd829 100644\n> --- a/hw/riscv/virt.c\n> +++ b/hw/riscv/virt.c\n> @@ -248,8 +248,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,\n>\n>          cpu_phandle = (*phandle)++;\n>\n> -        cpu_name = g_strdup_printf(\"/cpus/cpu@%d\",\n> -            s->soc[socket].hartid_base + cpu);\n> +        cpu_name = g_strdup_printf(\"/cpus/cpu@%\" PRIx32,\n> +            s->soc[socket].hartid_base + (uint32_t)cpu);\n>          qemu_fdt_add_subnode(ms->fdt, cpu_name);\n>\n>          if (satp_mode_max != -1) {\n>\n> --\n> 2.53.0\n>\n>","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Tu289g1w;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 09 Apr 2026\n 16:11:07 -0700 (PDT)","MIME-Version":"1.0","References":"<20260409-fix-unit-address-v1-0-946840930af2@iscas.ac.cn>\n <20260409-fix-unit-address-v1-5-946840930af2@iscas.ac.cn>","In-Reply-To":"<20260409-fix-unit-address-v1-5-946840930af2@iscas.ac.cn>","From":"Alistair Francis <alistair23@gmail.com>","Date":"Fri, 10 Apr 2026 09:10:40 +1000","X-Gm-Features":"AQROBzDXAHNGs9bJ86tYCUcUqXcY2fo0XK7RCn50bqQwvzx_rhA2w66un2AP4tE","Message-ID":"\n <CAKmqyKPO8HjaoLdC61rTiNkawFfwb6e9YtAq0c2YBcA-fTtXjQ@mail.gmail.com>","Subject":"Re: [PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes","To":"Vivian Wang <wangruikang@iscas.ac.cn>","Cc":"qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,\n  Leif Lindholm <leif.lindholm@oss.qualcomm.com>, qemu-arm@nongnu.org,\n  Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>,\n  Jiaxun Yang <jiaxun.yang@flygoat.com>, Paul Burton <paulburton@kernel.org>,\n  Aleksandar Rikalo <arikalo@gmail.com>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>,  Jia Liu <proljc@gmail.com>,\n Stafford Horne <shorne@gmail.com>,\n  Alistair Francis <Alistair.Francis@wdc.com>,\n Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liwei1518@gmail.com>,\n  Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n  Chao Liu <chao.liu.zevorn@gmail.com>, qemu-riscv@nongnu.org","Content-Type":"text/plain; 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