[{"id":3676484,"web_url":"http://patchwork.ozlabs.org/comment/3676484/","msgid":"","list_archive_url":null,"date":"2026-04-13T06:23:09","subject":"Re: [PATCH v2 2/3] hte: tegra194: Add Tegra264 GTE support","submitter":{"id":80054,"url":"http://patchwork.ozlabs.org/api/people/80054/","name":"Dipen Patel","email":"dipenp@nvidia.com"},"content":"On 4/8/26 2:24 PM, Suneel Garapati wrote:\n> Add AON-GTE mapping and LIC GTE instance support for the Tegra264.\n> Move TSC clock parameters from macros to members of SoC data\n> as values differ for Tegra264 chip.\n> \n> Signed-off-by: Suneel Garapati \n> ---\n> drivers/hte/hte-tegra194.c | 133 +++++++++++++++++++++++++++++++++++--\n> 1 file changed, 128 insertions(+), 5 deletions(-)\n> \n> diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c\n> index 690eb9be30fb..4a7702b32b24 100644\n> --- a/drivers/hte/hte-tegra194.c\n> +++ b/drivers/hte/hte-tegra194.c\n> @@ -20,10 +20,11 @@\n> \n> #define HTE_SUSPEND\t0\n> \n> -/* HTE source clock TSC is 31.25MHz */\n> +/* HTE source clock TSC is 1GHz for T264 and 31.25MHz for others */\n> #define HTE_TS_CLK_RATE_HZ\t31250000ULL\n> +#define HTE_TS_CLK_RATE_1G\t1000000000ULL\n> #define HTE_CLK_RATE_NS\t\t32\n> -#define HTE_TS_NS_SHIFT\t__builtin_ctz(HTE_CLK_RATE_NS)\n> +#define HTE_CLK_RATE_NS_1G\t1\n> \n> #define NV_AON_SLICE_INVALID\t-1\n> #define NV_LINES_IN_SLICE\t32\n> @@ -120,6 +121,8 @@ struct tegra_hte_data {\n> \tu32 slices;\n> \tu32 map_sz;\n> \tu32 sec_map_sz;\n> +\tu64 tsc_clkrate_hz;\n> +\tu32 tsc_clkrate_ns;\n> \tconst struct tegra_hte_line_mapped *map;\n> \tconst struct tegra_hte_line_mapped *sec_map;\n> };\n> @@ -317,6 +320,94 @@ static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {\n> \t[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},\n> };\n> \n> +static const struct tegra_hte_line_mapped tegra264_aon_gpio_map[] = {\n> +\t/* gpio, slice, bit_index */\n> +\t/* AA port */\n> +\t[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},\n> +\t[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},\n> +\t[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},\n> +\t[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},\n> +\t[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},\n> +\t[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},\n> +\t[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},\n> +\t[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},\n> +\t/* BB port */\n> +\t[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},\n> +\t[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},\n> +\t/* CC port */\n> +\t[10] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},\n> +\t[11] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},\n> +\t[12] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},\n> +\t[13] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},\n> +\t[14] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},\n> +\t[15] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},\n> +\t[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},\n> +\t[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},\n> +\t/* DD port */\n> +\t[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},\n> +\t[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},\n> +\t[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},\n> +\t[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},\n> +\t[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},\n> +\t[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},\n> +\t[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},\n> +\t[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},\n> +\t/* EE port */\n> +\t[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},\n> +\t[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},\n> +\t[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},\n> +\t[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},\n> +};\n> +\n> +static const struct tegra_hte_line_mapped tegra264_aon_gpio_sec_map[] = {\n> +\t/* gpio, slice, bit_index */\n> +\t/* AA port */\n> +\t[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},\n> +\t[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},\n> +\t[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},\n> +\t[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},\n> +\t[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},\n> +\t[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},\n> +\t[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},\n> +\t[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},\n> +\t/* BB port */\n> +\t[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},\n> +\t[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},\n> +\t[10] = {NV_AON_SLICE_INVALID, 0},\n> +\t[11] = {NV_AON_SLICE_INVALID, 0},\n> +\t[12] = {NV_AON_SLICE_INVALID, 0},\n> +\t[13] = {NV_AON_SLICE_INVALID, 0},\n> +\t[14] = {NV_AON_SLICE_INVALID, 0},\n> +\t[15] = {NV_AON_SLICE_INVALID, 0},\n> +\t/* CC port */\n> +\t[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},\n> +\t[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},\n> +\t[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},\n> +\t[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},\n> +\t[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},\n> +\t[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},\n> +\t[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},\n> +\t[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},\n> +\t/* DD port */\n> +\t[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},\n> +\t[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},\n> +\t[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},\n> +\t[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},\n> +\t[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},\n> +\t[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},\n> +\t[30] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},\n> +\t[31] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},\n> +\t/* EE port */\n> +\t[32] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},\n> +\t[33] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},\n> +\t[34] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},\n> +\t[35] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},\n> +\t[36] = {NV_AON_SLICE_INVALID, 0},\n> +\t[37] = {NV_AON_SLICE_INVALID, 0},\n> +\t[38] = {NV_AON_SLICE_INVALID, 0},\n> +\t[39] = {NV_AON_SLICE_INVALID, 0},\n> +};\n> +\n> static const struct tegra_hte_data t194_aon_hte = {\n> \t.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),\n> \t.map = tegra194_aon_gpio_map,\n> @@ -324,6 +415,8 @@ static const struct tegra_hte_data t194_aon_hte = {\n> \t.sec_map = tegra194_aon_gpio_sec_map,\n> \t.type = HTE_TEGRA_TYPE_GPIO,\n> \t.slices = 3,\n> +\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n> +\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n> };\n> \n> static const struct tegra_hte_data t234_aon_hte = {\n> @@ -333,6 +426,19 @@ static const struct tegra_hte_data t234_aon_hte = {\n> \t.sec_map = tegra234_aon_gpio_sec_map,\n> \t.type = HTE_TEGRA_TYPE_GPIO,\n> \t.slices = 3,\n> +\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n> +\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n> +};\n> +\n> +static const struct tegra_hte_data t264_aon_hte = {\n> +\t.map_sz = ARRAY_SIZE(tegra264_aon_gpio_map),\n> +\t.map = tegra264_aon_gpio_map,\n> +\t.sec_map_sz = ARRAY_SIZE(tegra264_aon_gpio_sec_map),\n> +\t.sec_map = tegra264_aon_gpio_sec_map,\n> +\t.type = HTE_TEGRA_TYPE_GPIO,\n> +\t.slices = 4,\n> +\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,\n> +\t.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,\n> };\n> \n> static const struct tegra_hte_data t194_lic_hte = {\n> @@ -340,6 +446,8 @@ static const struct tegra_hte_data t194_lic_hte = {\n> \t.map = NULL,\n> \t.type = HTE_TEGRA_TYPE_LIC,\n> \t.slices = 11,\n> +\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n> +\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n> };\n> \n> static const struct tegra_hte_data t234_lic_hte = {\n> @@ -347,6 +455,17 @@ static const struct tegra_hte_data t234_lic_hte = {\n> \t.map = NULL,\n> \t.type = HTE_TEGRA_TYPE_LIC,\n> \t.slices = 17,\n> +\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n> +\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n> +};\n> +\n> +static const struct tegra_hte_data t264_lic_hte = {\n> +\t.map_sz = 0,\n> +\t.map = NULL,\n> +\t.type = HTE_TEGRA_TYPE_LIC,\n> +\t.slices = 10,\n> +\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,\n> +\t.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,\n> };\n> \n> static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)\n> @@ -574,12 +693,12 @@ static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc,\n> static int tegra_hte_clk_src_info(struct hte_chip *chip,\n> \t\t\t\t struct hte_clk_info *ci)\n> {\n> -\t(void)chip;\n> +\tstruct tegra_hte_soc *hte_dev = chip->data;\n> \n> \tif (!ci)\n> \t\treturn -EINVAL;\n> \n> -\tci->hz = HTE_TS_CLK_RATE_HZ;\n> +\tci->hz = hte_dev->prov_data->tsc_clkrate_hz;\n> \tci->type = CLOCK_MONOTONIC;\n> \n> \treturn 0;\n> @@ -602,8 +721,10 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)\n> {\n> \tu32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id;\n> \tu64 tsc;\n> +\tu8 tsc_ns_shift;\n> \tstruct hte_ts_data el;\n> \n> +\ttsc_ns_shift = __builtin_ctz(gs->prov_data->tsc_clkrate_ns);\n> \twhile ((tegra_hte_readl(gs, HTE_TESTATUS) >>\n> \t\tHTE_TESTATUS_OCCUPANCY_SHIFT) &\n> \t\tHTE_TESTATUS_OCCUPANCY_MASK) {\n> @@ -621,7 +742,7 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)\n> \t\twhile (acv) {\n> \t\t\tbit_index = __builtin_ctz(acv);\n> \t\t\tline_id = bit_index + (slice << 5);\n> -\t\t\tel.tsc = tsc << HTE_TS_NS_SHIFT;\n> +\t\t\tel.tsc = tsc << tsc_ns_shift;\n> \t\t\tel.raw_level = tegra_hte_get_level(gs, line_id);\n> \t\t\thte_push_ts_ns(gs->chip, line_id, &el);\n> \t\t\tacv &= ~BIT(bit_index);\n> @@ -656,6 +777,8 @@ static const struct of_device_id tegra_hte_of_match[] = {\n> \t{ .compatible = \"nvidia,tegra194-gte-aon\", .data = &t194_aon_hte},\n> \t{ .compatible = \"nvidia,tegra234-gte-lic\", .data = &t234_lic_hte},\n> \t{ .compatible = \"nvidia,tegra234-gte-aon\", .data = &t234_aon_hte},\n> +\t{ .compatible = \"nvidia,tegra264-gte-lic\", .data = &t264_lic_hte},\n> +\t{ .compatible = \"nvidia,tegra264-gte-aon\", .data = &t264_aon_hte},\n> \t{ }\n> };\n> MODULE_DEVICE_TABLE(of, tegra_hte_of_match);\nReviewed-by: Dipen Patel ","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=YPrAX9Dt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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